Coordinating memory operations using memory-device generated reference signals

Patent metadata

Field	Value
Publication number	US-9384152-B2
Application number	US-201013577838-A
Country	US
Kind code	B2
Filing date	Dec 1, 2010
Priority date	Feb 23, 2010
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

First claim

What is claimed is:

1. A memory system, comprising:
a memory controller; and
a memory die coupled to the memory controller and comprising:
a memory data interface having a data pin coupled to the memory controller;
a data output circuit coupled to the data pin to transmit read data from the memory die to the memory controller, the data output circuit having a timing input to receive a timing-reference signal to time the transmitted read data; and
an integrated oscillator to generate the timing-reference signal within the memory die, the oscillator including at least one physical die structure that determines a frequency of the timing-reference signal, wherein the memory die is operable to coordinate a memory read operation with the memory controller and timed to the timing-reference signal.

2. The memory system of claim 1 , further comprising a reference transmitter to derive a shared reference signal from the timing-reference signal and to transmit the shared reference signal to the memory controller.

3. The memory system of claim 2 , wherein the reference transmitter transmits the shared reference signal to the memory controller via a dedicated, conductive reference signal path between the memory die and the memory controller.

4. The memory system of claim 2 , wherein the memory die is operable to divide down the frequency of the timing-reference signal to create the shared reference signal.

5. The memory system of claim 2 , wherein the memory controller is operable to coordinate at least one controller operation with the memory die based on the timing-reference signal.

6. The memory system of claim 2 , wherein the memory controller is operable to transmit write data to the memory die based on the shared reference signal.

7. The memory system of claim 6 , wherein the memory controller is operable to transmit a controller command to the memory die based on a processor reference signal.

8. The memory system of claim 7 , wherein the memory die further includes a memory core to perform a memory core operation based on the processor reference signal.

9. The memory system of claim 7 , wherein the memory die further includes a memory core, and wherein the memory die is operable to perform a memory core operation based on the timing-reference signal.

10. The memory system of claim 9 , wherein the memory controller is operable to program the memory die to generate the shared reference signal based on an approximate frequency ratio between the shared reference signal and the processor reference signal and to perform the memory core operation based on the shared reference signal.

11. The memory system of claim 10 , wherein the approximate frequency ratio is an integer.

12. The memory system of claim 6 , wherein the memory controller is operable to transmit a controller command to the memory die based on the shared reference signal.

13. The memory system of claim 12 , wherein the memory controller is operable to generate a divided down version of the timing-reference signal based on an approximate frequency ratio between the timing-reference signal and a processor reference signal and to transmit the controller command to the memory die based on the divided down version of the timing-reference signal.

14. The memory system of claim 13 , wherein the memory controller is operable to program the memory die to generate the shared reference signal and the memory die is operable to perform a memory core operation based on the shared reference signal.

15. The memory system of claim 13 , wherein the approximate frequency ratio is an integer.

16. The memory system of claim 1 , wherein the memory die comprises dynamic random access memory.

17. The memory system of claim 1 , wherein the oscillator comprises an LC clock circuit.

18. The memory system of claim 1 , wherein the memory die and the memory controller are embodied in first and second integrated circuits, respectively.

19. The memory system of claim 1 , wherein a combination of the memory die and the memory controller are embodied as a memory module.

20. The memory system of claim 1 , wherein the oscillator comprises a resonant LC oscillator circuit.

21. A memory die comprising:
a memory core;
a memory physical interface communicatively coupled to the memory core; and
an integrated oscillator operable to generate an internal reference signal of a frequency defined by a physical die structure of the memory die, the memory physical interface to transmit read data to an external die based on the internal reference signal.

22. The memory die of claim 21 , wherein the memory physical interface comprises a reference transmitter coupled to the oscillator, the reference transmitter to derive a shared reference signal from the internal reference signal and transmit the shared reference signal to the external die.

23. The memory die of claim 22 , wherein the shared reference signal is a periodic signal.

24. The memory die of claim 22 , wherein the shared reference signal has a shared frequency that is an integer fraction of the internal reference signal.

25. The memory die of claim 22 , wherein the memory physical interface comprises a memory data interface operable to receive write data that has been transmitted from the external die at second frequency derived from the internal reference signal.

26. The memory die of claim 25 , wherein the memory physical interface comprises a memory command interface operable to receive an external die command transmitted from the external die based on an external reference signal.

27. The memory die of claim 26 , wherein the memory physical interface is operable to receive the external reference signal and the memory die is operable to perform a memory core operation based on the received external reference signal.

28. The memory die of claim 26 , wherein the memory die is operable to perform a memory core operation based on the internal reference signal.

29. The memory die of claim 28 , wherein the external reference signal is of an external-reference frequency, and wherein the memory die comprises a core clock circuit operable to be programmed by the external die to divide the frequency of the internal reference signal to create a timing reference of the external-reference frequency.

30. The memory die of claim 29 , wherein the approximate ratio between the frequency of the internal reference signal and the external reference frequency is an integer.

31. The memory die of claim 25 , wherein the memory physical interface comprises a memory command interface operable to receive an external die command that has been transmitted from the external die at a bit rate, and wherein the frequency of the internal reference signal is an integer multiple of the bit rate.

32. The memory die of claim 31 , wherein the integer is greater than one.

33. The memory die of claim 32 , wherein the memory physical interface comprises a core clock circuit operable to be programmed by the external die to generate a divided down version of the internal reference signal.

34. The memory die of claim 21 , wherein the die structure includes an inductor of inductance L and exhibits a capacitance C, and wherein the frequency is the square root of 1/LC.

35. The memory die of claim 21

Assignees

• Best Scott C
• Shaeffer Ian
• Rambus Inc

Inventors

• Best Scott C
• Shaeffer Ian

Classifications

• G06F3/0683

  Plurality of storage devices · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title