Modification of prefetch depth based on high latency event

Patent metadata

Field	Value
Publication number	US-9384136-B2
Application number	US-201313861895-A
Country	US
Kind code	B2
Filing date	Apr 12, 2013
Priority date	Apr 12, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A prefetch stream is established in a prefetch unit of a memory controller for a system memory at a lowest level of a volatile memory hierarchy of the data processing system based on a memory access request received from a processor core. The memory controller receives an indication of an upcoming high latency event affecting access to the system memory. In response to the indication, the memory controller temporarily increases a prefetch depth of the prefetch stream with respect to the system memory and issues, to the system memory, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming high latency event.

First claim

What is claimed is:

1. A memory controller for controlling access to a system memory at a lowest level of a memory hierarchy of the data processing system, the memory controller comprising:
control logic that issues access requests to the system memory; and
a prefetch unit that establishes a prefetch stream based on a memory access request received from a processor core, wherein the prefetch unit, in response to receiving, during operation of the memory controller, an indication of an upcoming memory refresh cycle of the system memory that will temporarily increase access latency to the system memory, temporarily increases a prefetch depth of the prefetch stream with respect to the system memory and issues, to the control logic, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming memory refresh cycle.

2. The memory controller of claim 1 , wherein the memory access request of the processor core is a prefetch read request.

3. The memory controller of claim 2 , wherein the prefetch unit establishes the prefetch stream in response to the prefetch read request only if the prefetch read request is marked by a core prefetch unit as belonging to an extended prefetch stream.

4. The memory controller of claim 1 , wherein the prefetch unit grants the plurality of prefetch requests higher priority than at least one other prefetch request generated by the prefetch unit.

5. The memory controller of claim 1 , wherein:
the data processing system includes a system fabric; and
the prefetch unit, prior to issuing each prefetch request among the plurality of prefetch requests, obtains authority to obtain a copy of a target memory block of that prefetch request via communication on the system fabric.

6. The memory controller of claim 1 , wherein:
the memory controller further comprises prefetch buffers that buffer a plurality of target memory blocks obtained by the plurality of prefetch requests; and
the prefetch unit services a demand read request of the processor core by reference to the prefetch buffers.

7. The data processing system of claim 6 , wherein the processor core has an associated core prefetch unit.

8. The memory controller of claim 1 , wherein:
the memory access request is a first memory access request; and
the prefetch unit advances the prefetch stream in response to receipt of a second memory access request that hits in an address region of the prefetch stream.

9. A data processing system comprising:
the memory controller of claim 1 ; and
a processor core coupled to the memory controller.

10. The memory controller of claim 1 , wherein the memory controller, after temporarily increasing the prefetch depth of the prefetch stream, decreases the prefetch depth of the prefetch stream.

11. A design structure tangibly embodied in a non-transitory machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a memory controller for controlling access to a system memory at a lowest level of a memory hierarchy of the data processing system, the memory controller including:
control logic that issues access requests to the system memory; and
a prefetch unit that establishes a prefetch stream based on a memory access request received from a processor core, wherein the prefetch unit, in response to receiving, during operation of the memory controller, an indication of an upcoming memory refresh cycle of the system memory that will temporarily increase access to the system memory, temporarily increases a prefetch depth of the prefetch stream with respect to the system memory and issues, to the control logic, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming memory refresh cycle.

12. The design structure of claim 11 , wherein the design structure comprises a hardware description language (HDL) design structure.

13. The design structure of claim 11 , wherein the memory access request of the processor core is a prefetch read request.

14. The design structure of claim 13 , wherein the prefetch unit establishes the prefetch stream in response to the prefetch read request only if the prefetch read request is marked by a core prefetch unit as belonging to an extended prefetch stream.

15. The design structure of claim 11 , wherein the prefetch unit grants the plurality of prefetch requests higher priority than at least one other prefetch request generated by the prefetch unit.

16. The design structure of claim 11 , wherein:
the data processing system includes a system fabric; and
the prefetch unit, prior to issuing each prefetch request among the plurality of prefetch requests, obtains authority to obtain a copy of a target memory block of that prefetch request via communication on the system fabric.

17. The design structure of claim 11 , wherein:
the memory controller further comprises prefetch buffers that buffer a plurality of target memory blocks obtained by the plurality of prefetch requests; and
the prefetch unit services a demand read request of the processor core by reference to the prefetch buffers.

18. The design structure of claim 11 , wherein:
the memory access request is a first memory access request; and
the prefetch unit advances the prefetch stream in response to receipt of a second memory access request that hits in an address region of the prefetch stream.

19. The design structure of claim 11 , wherein the memory controller, after temporarily increasing the prefetch depth of the prefetch stream, decreases the prefetch depth of the prefetch stream.

Assignees

• IBM

Inventors

• Dodson John S
• Dooley Miles R
• Goodman Benjiman L
• Joyner Jody B
• Powell Stephen J
• Retter Eric E
• Stuecheli Jeffrey A

Classifications

• G06F9/383

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title