Code optimization to enable and disable coalescing of memory transactions

US9383930B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9383930-B2
Application numberUS-201514854574-A
CountryUS
Kind codeB2
Filing dateSep 15, 2015
Priority dateDec 12, 2013
Publication dateJul 5, 2016
Grant dateJul 5, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A transactional memory system controls the coalescing of outermost memory transactions. The coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. A processor of the transactional memory system executes a run-time instrumentation program for monitoring and modifying an associated program having a plurality of transactions. The processor initiates execution of the associated program. Based on execution of transactions, by the processor, of the associated program, the run-time instrumentation program dynamically obtains instrumentation information associated with the execution. Based on the obtained instrumentation information, the processor dynamically modifies continued execution of transactions of the associated program to optimize transactional execution (TX).

First claim

Opening claim text (preview).

What is claimed is: 1. A method of controlling a coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction, the method comprising: executing, by a processor, a run-time instrumentation program for monitoring and modifying an associated program having a plurality of transactions; initiating, by the processor, execution of the associated program; based on execution of transactions, by the processor, of the associated program, the run-time instrumentation program dynamically obtaining instrumentation information associated with the execution; and based on the obtained instrumentation information, dynamically modifying, by the processor, continued execution of transactions of the associated program to optimize transactional execution (TX) by adding a coalescing instruction that controls, at least in part, a coalescing of one or more outermost transactions, wherein the run-time instrumentation program modifying the continued execution of the associated program includes adding one or more coalescing instructions to the associated program to control coalescing of one or more of the plurality of transactions based, at least in part, on an analysis of gathered instrumentation information. 2. The method of claim 1 , the method further comprising: determining by the instrumentation program, that a first outermost transaction and a second outermost transaction of the plurality of transactions of the associated program should be coalesced; and coalescing transactions based on the determining. 3. The method of claim 1 , wherein executing the run-time instrumentation program includes: generating an environment for run-time profiling of the continued execution of the associated program for obtaining instrumentation information; and profiling the execution of the associated program using obtained instrumentation information and changes in a run-time environment of the associated program. 4. The method of claim 3 , the method further comprising: processing a run-time instrumentation directive of the run-time instrumentation program; and configuring a control of a run-time instrument based, at least in part, on the processed run-time instrumentation directive, wherein the run-time instrument includes one or more instructions to obtain instrumentation information regarding the execution of transactions of the associated program. 5. The method of claim 1 , wherein the one or more coalescing instructions include one or more of: (i) an instruction to coalesce outermost transactions, (ii) an instruction to remove a transaction begin or end instruction or to not execute a transaction begin or end instruction, (iii) an instruction to modify a transaction begin or end instruction such that an associated outermost transaction can-not be coalesced with a type of outermost transaction if a number of already coalesced instructions is greater than a threshold, (iv) an instruction to indicate that a particular outermost transaction is not-to-be coalesced with a type of outermost transaction if the number of already coalesced instructions is greater than the threshold, (v) an instruction to process non-transactional instructions as transactional instructions, (vi) an instruction to cease coalescing outermost transactions, and (vii) an instruction to specify a maximum allowable number of coalesced outermost transactions. 6. The method of claim 3 , wherein the obtained instrumentation information includes one or more of: (i) a reason for a coalesced outermost transaction being aborted, and a number of aborts it has received, (ii) a number of instructions between two coalesced outermost transactions, (iii) a type of instruction between two coalesced outermost transactions, (iv) whether any of the instructions between two coalesced outermost transactions are restricted from running in a given outermost transaction, (v) a number of dynamic instructions in a given outermost transaction, and (vi) a size of a footprint of a dynamic instruction in a given outermost transaction.

Assignees

Inventors

Classifications

  • with a shared cache · CPC title

  • G06F9/467Primary

    Transactional memory (G06F9/528 takes precedence) · CPC title

  • Intelligent editors · CPC title

  • Performance improvement · CPC title

  • Single storage device · CPC title

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Frequently asked questions

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What does patent US9383930B2 cover?
A transactional memory system controls the coalescing of outermost memory transactions. The coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. A processor of the transactional memory system executes a run-time instrumentation program for monitoring and modifying an associated program having a…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F9/467. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).