Thin-film transistor, method for manufacturing the same and display device comprising the same

Patent metadata

Field	Value
Publication number	US-9379249-B2
Application number	US-201414219385-A
Country	US
Kind code	B2
Filing date	Mar 19, 2014
Priority date	Mar 29, 2013
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A thin-film transistor includes a substrate, a first gate electrode formed on the substrate, a first active layer that is formed on the substrate and includes a first oxide semiconductor layer and a first barrier layer, a second active layer that is formed on the first active layer and includes a second oxide semiconductor layer and an intermediate barrier layer, a gate insulating layer that is formed on the second active layer, a second gate electrode that is formed on the gate insulating layer and is electrically connected to the first gate electrode, an interlayer insulating film formed on the second gate electrode, the first active layer and the second active layer, and a source electrode and a drain electrode electrically connected to the first active layer and the second active layer.

First claim

What is claimed is:

1. A thin-film transistor, comprising:
a first gate electrode;
a first gate insulating layer on the first gate electrode;
a first oxide semiconductor layer and a second oxide semiconductor layer on the first gate insulating layer, the first and second oxide semiconductor layers providing a lower channel and an upper channel, respectively, wherein the second oxide semiconductor layer has a smaller area than an area of the first oxide semiconductor layer to enhance current flow of the thin-film transistor;
an intermediate barrier layer separating the first and second oxide semiconductor layers, the intermediate barrier layer forming a charge trapping barrier obstructing a transport of charge between the first and second oxide semiconductor layers, wherein the intermediate barrier layer has a maximum valence band value (Vmax) lower than a maximum valence band value (Vmax) of the first and second oxide semiconductor layers to prevent holes or electrons in the first and second oxide semiconductor layers from being trapped to the first gate insulating layer;
a second gate insulating layer on the second oxide semiconductor layer having a same width as that of the second oxide semiconductor layer comprising a smaller area than an area of the first oxide semiconductor layer;
a second gate electrode on the second gate insulating layer, the second gate electrode electrically connected to the first gate electrode;
a source electrode electrically connected to the first and second oxide semiconductor layers; and
a drain electrode electrically connected to the first and second oxide semiconductor layers.

2. The thin-film transistor of claim 1 , wherein the first oxide semiconductor layer is controlled by a first voltage applied to the first gate electrode and the second oxide semiconductor layer is controlled by a second voltage applied to the second gate electrode.

3. The thin-film transistor of claim 2 , wherein the first and second voltages are identical.

4. The thin-film transistor of claim 1 , wherein the intermediate barrier layer has a maximum conduction band value (Cmax) greater than the maximum conduction band value (Cmax) of first and second oxide semiconductor layers when the thin-film transistor is a P-type thin-film transistor.

5. The thin-film transistor of claim 1 , wherein the first oxide semiconductor layer has a cross-sectional width equal to or greater than that of the second oxide semiconductor layer, and wherein the source and drain electrodes are in direct contact with the first and second oxide semiconductor layers.

6. The thin-film transistor of claim 1 , further comprising at least one of:
a first barrier layer interposed between the first gate insulating layer and the first oxide semiconductor layer; and
a second barrier layer interposed between the second gate insulating layer and the second oxide semiconductor layer.

7. The thin-film transistor of claim 6 , wherein the first barrier layer has a maximum valence band value (Vmax) lower than that of the first oxide semiconductor layer and the first gate insulating layer when the thin-film transistor is an N-type thin-film transistor, and wherein the first barrier layer has a maximum conduction band value (Cmax) greater than that of the first oxide semiconductor layer and the first gate insulating layer when the thin-film transistor is a P-type thin-film transistor.

8. The thin-film transistor of claim 6 , wherein the second barrier layer has a maximum valence band value (Vmax) lower than that of the second oxide semiconductor layer and the second gate insulating layer when the thin-film transistor is an N-type thin-film transistor, and wherein the second barrier layer has a maximum conduction band value (Cmax) greater than that of the second oxide semiconductor layer and the second gate insulating layer when the thin-film transistor is a P-type thin-film transistor.

9. The thin-film transistor of claim 1 , wherein the first gate electrode is made of a reflective conductive material.

10. The thin-film transistor of claim 1 , wherein, when the thin-film transistor is an N-type thin-film transistor, the intermediate barrier layer includes at least one of a TiOx, TaOx, SrTiO 3 , BaZrO 3 , ZrO 2 , HfO 2 , Al 2 O 3 , MgO, Ga 2 O 3 , and wherein, when the thin-film transistor is an P-type thin-film transistor, the intermediate barrier layer includes at least one of Cu 2 O, CuAlO 2 , SiO 2 , SrCu 2 O 2 , Al 2 O 3 .

11. A method for manufacturing a thin-film transistor, the method comprising: forming a first gate electrode on a substrate:
forming a first gate insulating layer on the first gate electrode;
forming a first oxide semiconductor layer and a second oxide semiconductor layer on the first gate insulating layer, the first and second oxide semiconductor layers providing a lower channel and an upper channel, respectively, wherein the second oxide semiconductor layer has a smaller area than an area of the first oxide semiconductor layer to enhance current flow of the thin-film transistor;
forming an intermediate barrier layer for separating the first and second oxide semiconductor layers, the intermediate barrier layer having a charge trapping barrier for obstructing a transport of charge between the first and second oxide semiconductor layers, wherein the intermediate barrier layer has a maximum valence band value (Vmax) lower than a maximum valence band value (Vmax) of the first and second oxide semiconductor layers to prevent holes or electrons in the first and second oxide semiconductor layers from being trapped to the first gate insulating layer;
forming a second gate insulating layer on the second oxide semiconductor layer having a same width as that of the second oxide semiconductor layer comprising a smaller area than an area of the first oxide semiconductor layer;
forming a second gate electrode on the second gate insulating layer, the second gate electrode electrically connected to the first gate electrode;
forming a source electrode electrically connected to the first and second oxide semiconductor layers; and
forming a drain electrode electrically connected to the first and second oxide semiconductor layers.

12. The method of claim 11 , wherein the first oxide semiconductor layer is controlled by a first voltage applied to the first gate electrode and the second oxide semiconductor layer is controlled by a second voltage applied to the second gate electrode.

13. The method of claim 12 , wherein the first and second voltages are identical.

14. The method of claim 11 , wherein the intermediate barrier layer has a maximum conduction band value (Cmax) greater than the maximum conduction band value (Cmax) of first and second oxide semiconductor layers when the thin-film transistor is a P-type thin-film transistor.

15. The method of claim 11 , wherein the first oxide semiconductor layer has a cross-sectional width equal to or greater than that of the second oxide semiconductor layer, and wherein the source and drain electrodes are in direct contact with the first and second oxide semiconductor layers.

16. The method of claim 11 , further comprising:
forming a first barrier layer interposed between the first gate insulating layer and the first oxide semiconductor layer; and
forming a second barrier layer interposed between the second gate insulating layer and the second oxide semiconductor layer.

17. The method of claim 16 , wherein the first barrier layer has a maximum valence band value (Vmax) lower than that of the first oxide semiconductor layer and the first gate insulating layer

Assignees

• Lg Display Co Ltd

Inventors

• Ji Kwanghwan
• Kim Daehwan
• Bae Junhyeon

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734 Primary

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title