Semiconductor device having fin-type field effect transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9379244-B2
Application number	US-201514668490-A
Country	US
Kind code	B2
Filing date	Mar 25, 2015
Priority date	Apr 25, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate; and
a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate,
wherein the first and third buffer patterns comprise a first semiconductor layer including germanium (Ge), the first channel pattern comprises a second semiconductor layer including germanium (Ge), and the second channel pattern comprises a third semiconductor layer including germanium (Ge), and
wherein a germanium (Ge) concentration of the first semiconductor layer is less than germanium (Ge) concentrations of the second and third semiconductor layers.

2. The semiconductor device of claim 1 , wherein the second buffer pattern comprises a fourth semiconductor layer including germanium (Ge), and
wherein a difference of germanium (Ge) concentrations between the first channel pattern and an upper portion of the second buffer pattern is less than a difference of germanium (Ge) concentrations between the second channel pattern and an upper portion of the third buffer pattern.

3. The semiconductor device of claim 1 , wherein the second buffer pattern comprises a semiconductor material including germanium (Ge), a germanium (Ge) concentration of the second buffer pattern progressively increasing from a bottom portion of the second buffer pattern to an upper portion of the second buffer pattern,
wherein the first semiconductor layer has a first germanium (Ge) concentration, the first germanium (Ge) concentration being substantially the same as the germanium (Ge) concentration of the bottom portion of the second buffer pattern, and
wherein the second semiconductor layer has a second germanium (Ge) concentration, the second germanium (Ge) concentration being substantially the same as the germanium (Ge) concentration of the upper portion of the second buffer pattern.

4. The semiconductor device of claim 1 , wherein the first semiconductor layer has a first germanium (Ge) concentration, the first germanium (Ge) concentration being substantially constant in the first semiconductor layer; and
wherein the third semiconductor layer has a second germanium (Ge) concentration greater than the first germanium (Ge) concentration.

5. The semiconductor device of claim 1 , wherein the first semiconductor layer comprises Si 1−x Ge x (0<x<1), the second semiconductor layer comprises Si 1−y Ge y (x≦y≦1), and the third semiconductor layer comprises Si 1−a Ge a (x<a≦1).

6. The semiconductor device of claim 1 , wherein an upper surface of the first buffer pattern has a level lower than that of an upper surface of the third buffer pattern.

7. The semiconductor device of claim 1 , wherein an upper surface of the first channel pattern has a substantially same level as an upper surface of the second channel pattern from the substrate, and
wherein an upper surface of the second buffer pattern has a substantially same level as an upper surface of the third buffer pattern from the substrate.

8. The semiconductor device of claim 1 , wherein an upper surface of the first channel pattern has a substantially same level as an upper surface of the second channel pattern from the substrate, and
wherein an upper surface of the second buffer pattern has a lower level than an upper surface of the third buffer pattern from the substrate.

9. The semiconductor device of claim 1 , wherein the substrate comprises single crystal silicon,
wherein the first and second channel patterns comprise an epitaxial layer having upper surfaces parallel to an upper surface of the substrate and sidewalls substantially perpendicular to the upper surface of the substrate, and
wherein the sidewalls of the first and second channel patterns have a (110) or (111) crystal orientation.

10. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate; and
a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate,
wherein the first and second channel patterns comprise a semiconductor material including germanium (Ge), and
wherein a difference of lattice constants at a first interface between the first channel pattern and an upper portion of the second buffer pattern is less than a difference of lattice constants at a second interface between the second channel pattern and an upper portion of the third buffer pattern.

11. The semiconductor device of claim 10 , wherein the first buffer pattern and the third buffer pattern comprise substantially the same semiconductor material, the first buffer pattern and the third buffer pattern having a lattice constant greater than that of the substrate.

12. The semiconductor device of claim 10 , wherein an upper surface of the first buffer pattern has a lower level than an upper surface of the third buffer pattern from the substrate.

13. The semiconductor device of claim 10 , wherein the first and third buffer patterns comprise silicon germanium (SiGe), and wherein germanium concentrations of the first and third buffer patterns are less than germanium concentrations of the first and second channel patterns, respectively.

14. The semiconductor device of claim 10 , wherein the first buffer pattern, the second buffer pattern, and the first channel pattern comprise silicon germanium (SiGe),
wherein a germanium (Ge) concentration of the second buffer pattern progressively increases from a bottom portion of the second buffer pattern to an upper portion of the second buffer pattern, and
wherein the first buffer pattern has a first uniform germanium (Ge) concentration, the first uniform germanium (Ge) concentration being substantially the same as the germanium (Ge) concentration of the bottom portion of the second buffer pattern.

15. The semiconductor device of claim 14 , wherein the first channel pattern has a second uniform germanium (Ge) concentration, the second uniform germanium (Ge) concentration being substantially the same as a germanium (Ge) concentration of the upper portion of the second buffer pattern.

16. The semiconductor device of claim 10 , wherein the third buffer pattern and the second channel pattern comprise silicon germanium (SiGe),
wherein the third buffer pattern has a first uniform germanium (Ge) concentration and the second channel pattern has a second uniform germanium (Ge) concentration, the second uniform germanium (Ge) concentration being greater than the first uniform germanium (Ge) concentration.

17. A semiconductor device, comprising:
a substrate including first and second side-by-side regions; and
first and second metal-oxide-semiconductor (MOS) transistors comprising first and second fin structures on the first and second regions of the substrate, respectively, wherein:
the first fin structure comp

Assignees

• Hur Sung Gi
• Kwon Taeyong
• Kim Sangsu
• Choi Jungdal
• Samsung Electronics Co Ltd

Inventors

• Hur Sung Gi
• Kwon Taeyong
• Kim Sangsu
• Choi Jungdal

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title