Semiconductor device with strained channels

Patent metadata

Field	Value
Publication number	US-9379241-B2
Application number	US-201514869546-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Aug 18, 2006
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate including a device region in the substrate and isolation regions in the substrate adjacent to the device region, wherein a deepest part of the isolation regions is at an isolation region depth;
the device region including a first source/drain region in the substrate, a second source/drain region in the substrate, and a channel region in the substrate between the first source/drain region and the second source drain region, wherein a deepest part of the first and second source/drain regions is at a source/drain region depth;
the isolation regions being formed in isolation trenches having inner trench walls proximate to the device region and opposing outer trench walls, wherein an oxide is on the outer trench walls and is not on the inner trench walls;
the isolation regions having strain-inducing regions laterally adjacent to the channel region, wherein portions of the isolation regions have adjusted volumes laterally adjusting an inner extent of the strain inducing regions with respect to the inner trench walls to strain the channel region, and wherein a deepest part of the strain-inducing regions is at a strain-inducing depth, both the isolation region depth and the source/drain region depth being deeper than the strain-inducing region depth; and
the channel region including a strain induced by the strain-inducing regions in the isolation regions.

2. The structure of claim 1 , wherein the strain-inducing regions include implanted helium ions.

3. The structure of claim 1 , wherein the strain-inducing regions include nanocavities.

4. The structure of claim 3 , wherein the strain-inducing regions include an oxide.

5. The structure of claim 4 , wherein the oxide includes silicon dioxide.

6. The structure of claim 4 , wherein the strain-inducing regions include an oxide formed using implanted oxygen ions.

7. The structure of claim 1 , wherein the strain-inducing regions includes implanted argon ions.

8. The structure of claim 1 , wherein the strain-inducing regions includes implanted hydrogen ions.

9. The structure of claim 1 , wherein the strain-inducing regions includes implanted argon ions and implanted hydrogen ions.

10. The structure of claim 1 , wherein the channel region includes a tensile strain.

11. The structure of claim 10 , wherein the tensile strain is within a range of approximately 0.75% to approximately 1.5%.

12. The structure of claim 1 , wherein the channel region includes a compressive strain.

13. The structure of claim 12 , wherein the compressive strain is within a range of approximately 0.2% to approximately 1.0%.

14. The structure of claim 1 , wherein the strain is a predominantly uniaxial strain.

15. The structure of claim 1 , wherein the strain is a predominantly biaxial strain.

16. The structure of claim 1 , further comprising an epitaxial semiconductor layer on the device region and the isolation region.

17. A semiconductor structure, comprising:
a semiconductor substrate including a p-channel device, including a p-channel device region in the substrate and p-channel isolation regions in the substrate on opposing sides of the p-channel device region, the p-channel device region including first and second source/drain regions in the substrate and a p-channel region in the substrate between the first and second source drain regions, the p-channel isolation regions being formed in p-channel isolation trenches having inner p-channel trench walls proximate to the p-channel device region and an opposing outer p-channel trench walls, wherein an oxide is on the outer p-channel trench walls and is not on the inner p-channel trench walls, wherein portions of the p-channel isolation regions have adjusted volumes laterally adjusting toward the p-channel device region an inner extent of the p-channel isolation region with respect to the inner trench walls to provide strain-inducing regions laterally adjacent to the p-channel region, wherein a deepest part of the p-channel isolation regions is at a p-channel isolation region depth, a deepest part of the first and second source/drain regions of the p-channel device is at a p-channel source/drain region depth, and a deepest part of the strain-inducing regions of the p-channel isolation regions is at a p-channel strain-inducing depth, both the p-channel isolation region depth and the p-channel source/drain region depth being deeper than the p-channel strain-inducing depth, and the p-channel region including a compressive strain induced by the strain-inducing regions in the p-channel isolation regions; and
the semiconductor substrate further including an n-channel device, including an n-channel device region in the substrate and n-channel isolation regions in the substrate on opposing sides of the n-channel device region, the n-channel device region including first and second source/drain regions in the substrate and a n-channel region in the substrate between the first and second source drain regions, the n-channel isolation regions being formed in n-channel isolation trenches having inner n-channel trench walls proximate to the n-channel device region and an opposing outer n-channel trench walls, wherein an oxide is on the outside n-channel trench walls and is not on the inner trench walls, wherein portions of the n-channel isolation regions have adjusted volumes laterally adjusting toward the n-channel device region an inner extent of the n-channel isolation region with respect to the inner trench walls to provide strain-inducing regions laterally adjacent to the n-channel region, wherein a deepest part of the n-channel isolation regions is at a n-channel isolation region depth, a deepest part of the first and second source/drain regions of the n-channel device is at a n-channel source/drain region depth, and a deepest part of the strain-inducing regions of the n-channel isolation regions is at a n-channel strain-inducing depth, both the n-channel isolation region depth and the n-channel source/drain region depth being deeper than the n-channel strain-inducing depth, and the n-channel region including a tensile strain induced by the strain-inducing regions in the n-channel isolation regions.

18. The structure of claim 17 , wherein the strain-inducing regions of the n-channel isolation regions and the p-channel isolation regions include implanted helium ions.

19. The structure of claim 18 , wherein the strain-inducing regions of the p-channel isolation regions include an oxide formed using implanted oxygen ions.

20. The structure of claim 18 , wherein the strain-inducing regions of the n-channel isolation regions include implanted argon ions.

21. The structure of claim 20 , wherein the strain-inducing regions of the n-channel isolation regions include implanted hydrogen ions.

22. The structure of claim 17 , further comprising an epitaxial silicon layer on the p-channel isolation regions and the n-channel isolation regions.

23. The structure of claim 22 , wherein the strain-inducing regions of the p-channel isolation regions include implanted helium ions.

24. The structure of claim 22 , wherein the strain-inducing regions of the n-channel isolation regions include implanted argon ions.

25. The structure of claim 22 , wherein the strain-inducing regions of the n-channel isolation regions include implanted hydrogen ions.

26. A semiconductor structure, comprising:
a

Assignees

• Micron Technology Inc

Inventors

• Bhattacharyya Arup
• Forbes Leonard
• Farrar Paul A

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/0124

  the regions having non-rectangular shapes, e.g. rounded (H10W10/0123 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title