Electrostatic discharge diodes and methods of forming electrostatic discharge diodes

Patent metadata

Field	Value
Publication number	US-9379201-B2
Application number	US-201514805745-A
Country	US
Kind code	B2
Filing date	Jul 22, 2015
Priority date	May 6, 2013
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

First claim

What is claimed is:

1. A method comprising:
thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate; and
forming a first metal-semiconductor junction diode at the back-side of the substrate, wherein the first metal-semiconductor junction diode is coupled to the first via.

2. The method of claim 1 , further comprising:
patterning an opening in an isolation layer deposited on the back-side of the substrate, wherein the opening exposes the substrate; and
depositing a redistribution layer in the opening, wherein the first metal-semiconductor junction diode is formed based on the redistribution layer contacting the substrate through the opening, and wherein the redistribution layer couples the first metal-semiconductor junction diode to the first via.

3. The method of claim 1 , wherein thinning the back-side of the substrate further exposes a portion of a second via in the substrate, and wherein a second metal-semiconductor junction diode is coupled to the second via.

4. The method of claim 3 , further comprising:
depositing an n-type semiconductor material on the second via; and
depositing a redistribution layer on the n-type semiconductor material, wherein the second metal-semiconductor junction diode is formed based on the redistribution layer contacting the n-type semiconductor material.

5. The method of claim 3 , wherein the first metal-semiconductor junction diode and the second metal-semiconductor junction diode have substantially opposite polarities.

6. The method of claim 1 , wherein the first metal-semiconductor junction diode comprises a Schottky barrier diode.

7. The method of claim 1 , wherein the first metal-semiconductor junction diode is configured to sink electrostatic charges into the substrate.

8. A method comprising:
a step for thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate; and
a step for forming a metal-semiconductor junction diode at the back-side of the substrate, wherein the metal-semiconductor junction diode is coupled to the first via.

9. The method of claim 8 , wherein the step for thinning and the step for forming are performed by a processor integrated into an electronic device.

10. An apparatus formed by a process comprising:
thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate; and
forming a first metal-semiconductor junction diode at the back-side of the substrate, wherein the first metal-semiconductor junction diode is coupled to the first via.

11. The apparatus of claim 10 , wherein the process further comprises:
patterning an opening in an isolation layer deposited on the back-side of the substrate, wherein the opening exposes the substrate; and
depositing a redistribution layer in the opening, wherein the first metal-semiconductor junction diode is formed based on the redistribution layer contacting the substrate through the opening, and wherein the redistribution layer couples the first metal-semiconductor junction diode to the first via.

12. The apparatus of claim 10 , wherein thinning the back-side of the substrate further exposes a portion of a second via that is formed in the substrate, and wherein a second metal-semiconductor junction diode is coupled to the second via.

13. The apparatus of claim 12 , wherein the process further comprises:
depositing an n-type semiconductor material on the second via; and
depositing a redistribution layer on the n-type semiconductor material, wherein the second metal-semiconductor junction diode is formed based on the redistribution layer contacting the n-type semiconductor material.

14. The apparatus of claim 12 , wherein the first metal-semiconductor junction diode and the second metal-semiconductor junction diode have substantially opposite polarities.

15. The apparatus of claim 10 , wherein the first metal-semiconductor junction diode comprises a Schottky barrier diode.

16. The apparatus of claim 10 , wherein the first metal-semiconductor junction diode is configured to sink electrostatic charges into the substrate.

Assignees

• Qualcomm Inc

Inventors

• Ramachandran Vidhya
• Henderson Brian Matthew
• Gu Shiqun
• Tan Chiew-Guan
• Kim Jung Pill
• Kim Taehyun

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title