Method of forming a trench using epitaxial lateral overgrowth and deep vertical trench structure

Patent metadata

Field	Value
Publication number	US-9379196-B2
Application number	US-201414174185-A
Country	US
Kind code	B2
Filing date	Feb 6, 2014
Priority date	Feb 6, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a first surface;
a first dielectric layer arranged on the first surface and comprising first openings;
an epitaxial layer filling the first openings and extending onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap between opposing sidewalls of the epitaxial layer is over the part of the first dielectric layer that is uncovered by the epitaxial layer, the gap defining a first trench in the epitaxial layer that extends to the first dielectric layer;
a first conductive electrode arranged in the first trench; and
a trench dielectric arranged in the first trench and electrically insulating the first electrode from the adjacent semiconductor material.

2. The semiconductor device of claim 1 , further comprising:
a second trench arranged in the epitaxial layer and spaced apart from the first trench, the second trench extending towards the first surface of the semiconductor substrate;
wherein an outer surface of the epitaxial layer extends from one of the opposing sidewalls to the second trench and is inclined with respect to the first surface.

3. The semiconductor device of claim 2 , further comprising:
a second conductive electrode arranged in the second trench.

4. The semiconductor device of claim 3 , wherein the first conductive electrode forms a gate electrode of a MOSFET device and the second conductive electrode forms a source contact of the MOSFET device.

5. The semiconductor device of claim 3 , wherein the trench dielectric extends outside of the first trench along the outer surface to the second trench.

6. The semiconductor device of claim 1 , wherein the opposing sidewalls comprise an atomically flat surface.

7. A semiconductor device, comprising:
a semiconductor substrate having a first surface;
a first dielectric layer arranged on the first surface and comprising first openings;
an epitaxial layer filling the first openings and extending onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap between opposing sidewalk of the epitaxial layer is over the part of the first dielectric layer that is uncovered by the epitaxial layer, the gap defining a first trench in the epitaxial layer that extends to the first dielectric layer; and
a second trench arranged in the epitaxial layer and spaced apart from the first trench, the second trench extending towards the first surface of the semiconductor substrate,
wherein an outer surface of the epitaxial layer extends from one of the opposing sidewalls to the second trench and is inclined with respect to the first surface.

8. The semiconductor device of claim 7 , further comprising:
a first conductive electrode arranged in the first trench; and
a second conductive electrode arranged in the second trench;
a trench dielectric arranged in the first trench and electrically insulating the first electrode from the adjacent semiconductor material.

9. The semiconductor device of claim 8 , wherein the first conductive electrode forms a gate electrode of a MOSFET device and the second conductive electrode forms a source contact of the MOSFET device.

10. The semiconductor device of claim 8 , wherein the trench dielectric extends outside of the first trench along the outer surface to the second trench.

Assignees

• Infineon Technologies Austria

Inventors

• Joshi Ravi
• Baumgartl Johannes
• Poelzl Martin
• Kuenle Matthias
• Steinbrenner Juergen
• Haghofer Andreas
• Gruber Christoph
• Ehrentraut Georg

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/642 Primary

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title