Method of forming channel region dopant control in fin field effect transistor

Patent metadata

Field	Value
Publication number	US-9379185-B2
Application number	US-201414260953-A
Country	US
Kind code	B2
Filing date	Apr 24, 2014
Priority date	Apr 24, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions may be formed. A planarization dielectric layer is formed over the at least one semiconductor fin, and the dummy gate structure is removed to provide a gate cavity. Electrical dopants in the channel region can be removed by outgassing during an anneal, thereby lowering the concentration of the electrical dopants in the channel region. Alternately or additionally, carbon can be implanted into the channel region to deactivate remaining electrical dopants in the channel region. The threshold voltage of the field effect transistor can be effectively controlled by the reduction of active electrical dopants in the channel region. A replacement gate electrode can be subsequently formed in the gate cavity.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a semiconductor fin on a substrate, said semiconductor fin including atoms of an electrical dopant of a conductivity type throughout an entirety thereof, said conductivity type selected from p-type and n-type;
forming a planarization dielectric layer over said at least one semiconductor fin;
forming a cavity straddling said semiconductor fin in said planarization dielectric layer, said cavity exposing a body a portion of said semiconductor fin; and
evaporating, after forming said cavity, a subset of said atoms of said electrical dopant from said body portion of said semiconductor fin, said evaporating comprises exposing said body portion of said semiconductor fin to an ambient in an anneal process.

2. The method of claim 1 , further comprising forming a gate structure including a gate dielectric and a gate electrode within said cavity.

3. The method of claim 2 , further comprising forming a disposable gate structure straddling said semiconductor fin, wherein said planarization dielectric layer is formed on said disposable gate structure.

4. The method of claim 3 , further comprising removing said disposable gate structure selective to said semiconductor fin and said planarization dielectric layer, wherein said cavity is formed in a volume from which said disposable gate structure is removed.

5. The method of claim 3 , further comprising forming a source region and a drain region in said semiconductor tin, wherein atoms of another electrical dopant having another conductivity type that is the opposite of said conductivity type are present in each of said source region and said drain region at a greater concentration than a concentration, prior to said anneal process, of atoms of said electrical dopant of said conductivity type in said semiconductor fin.

6. The method of claim 1 , wherein said atoms of said electrical dopant are present at a same concentration throughout an entirety of said semiconductor fin prior to said anneal process.

7. The method of claim 1 , wherein a concentration of atoms of said electrical dopant is lesser, after said anneal process, in said body portion of said semiconductor fin underlying said cavity than in another portion of said semiconductor fin that does not underlie said cavity.

8. The method of claim 1 , further comprising forming a raised source region and a raised drain region by depositing a semiconductor material on surfaces of said semiconductor fin prior to forming said planarization dielectric layer.

9. The method of claim 8 , further comprising doping said raised source region and raised drain region with atoms of another electrical dopant having another conductivity type that is the opposite of said conductivity type.

10. The method of claim 9 , wherein said atoms of said another electrical dopant having another conductivity type are introduced into said raised source region and said raised drain region at a greater concentration than a concentration, prior to said anneal process, of said atoms of said electrical dopant of said conductivity type in said semiconductor fin.

11. The method of claim 1 , wherein said body portion of said semiconductor fin underlying said cavity has a concentration of atoms of said electrical dopant of said conductivity type at a concentration that is less than 10 % of a concentration of atoms of said electrical dopant of said conductivity type in a region that does not underlie said cavity.

12. The method of claim 1 , wherein said ambient includes hydrogen gas and nitrogen gas, and said anneal process is performed at a temperature greater than 700 degrees Celsius.

13. The method of claim 1 , further comprising forming, a pair of p-n junctions in said semiconductor fin by doping end portions of said semiconductor fin with atoms of another electrical dopant of another conductivity type that is the opposite of said conductivity type, wherein a distance between said p-n junctions decreases during said anneal process.

14. The method of claim 1 , further comprising implanting carbon into said portion of said semiconductor fin underlying said cavity while said cavity is present.

Assignees

• IBM

Inventors

• Chowdhury Murshed M
• Greene Brian J
• Kumar Arvind

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P36/03

  within silicon bodies · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10P30/208

  of electrically inactive species · CPC title