Magneto-elastic non-volatile multiferroic logic and memory with ultralow energy dissipation

Patent metadata

Field	Value
Publication number	US-9379162-B2
Application number	US-201414546393-A
Country	US
Kind code	B2
Filing date	Nov 18, 2014
Priority date	Nov 18, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Memory cells, non-volatile logic gates, and combinations thereof have magneto-tunneling junctions (MTJs) which are switched using potential differences across a piezoelectric layer in elastic contact with a magnetostrictive nanomagnet of an MTJ. One or more pairs of electrodes are arranged about the MTJ for supplying voltage across the piezoelectric layer for switching. A permanent magnetic field may be employed to change the positions of the stable magnetic orientations of the magnetostrictive nanomagnet. Exemplary memory cells and universal non-volatile logic gates show dramatically improved performance characteristics, particularly with respect to energy dissipation and error-resilience, over existing methods and architectures for switching MTJs such as spin transfer torque (STT) techniques.

First claim

What is claimed is:

1. A non-volatile magneto-elastic memory cell, comprising:
a substrate over which a piezoelectric film is deposited, wherein the substrate is conductive or an additional conducting layer is interposed between the substrate and the piezoelectric film;
a magneto-tunneling junction (MTJ) formed on the piezoelectric film comprising a hard magnetic layer, a spacer layer, and a soft magnetic layer,
wherein the hard magnetic layer is permanently magnetized along one direction,
wherein the soft magnetic layer consists of a magnetostrictive nanomagnet in elastic contact with the piezoelectric film and has a magnetization vector with two stable orientations that are more than 90° apart; and

at least two pairs of electrodes arranged over the piezoelectric film, wherein a line joining the members of a first pair of electrodes and a line joining the members of a second pair of electrodes cross the soft magnetic layer,
wherein the line joining the members of the first pair of electrodes and the line joining the members of the second pair of electrodes are non-parallel to one another and to the two stable orientations of the magnetization vector of the soft magnetic layer,
wherein sequential applications of voltage to the at least two pairs of electrodes generate electric fields causing a strain in the piezoelectric film, said strain being transferred to the soft magnetic layer causing a rotation of the magnetization vector from one of the two stable orientations to the other, thereby changing a resistance of the MTJ from a high state to a low state or from the low state to the high state,
wherein the first pair of electrodes is arranged so that the application of a first voltage to the first pair of electrodes generates an electric field which causes a first strain in the piezoelectric film, the first strain being transferred to the soft magnetic layer so as to cause a rotation of the magnetization vector to a first intermediate orientation that subtends an angle of 90° or less with an initial stable orientation of the magnetization vector,
wherein the last pair of electrodes is arranged so that the application of a voltage to the last pair of electrodes generates another electric field which causes another strain in the piezoelectric film, the strain being transferred to the soft magnetic layer so as to cause further rotation of the magnetization vector to an intermediate orientation that subtends an angle of greater than 90° with the initial stable orientation of the magnetization vector, and
wherein upon removal of stress from the last pair of electrodes the magnetization decays to the second stable orientation, and
wherein one of the stable orientations encodes a binary bit of “0” and the other a binary bit of “1”.

2. The non-volatile magneto-elastic memory cell of claim 1 , wherein the line joining the members of the first pair of electrodes and the line joining the members of the second pair of electrodes pass through a center of the soft magnetic layer.

3. The non-volatile magneto-elastic memory cell of claim 1 , wherein the soft magnetic layer is an ellipse, rectangle, parallelogram, or any other shape with two stable magnetization orientations.

4. The non-volatile magneto-elastic memory cell of claim 1 , wherein members of each pair of the at least two pairs of electrodes are electrically shorted with one another.

5. The non-volatile magneto-elastic memory cell of claim 1 , wherein the two stable orientations of the magnetization vector of the soft magnetic layer are substantially 180° apart.

6. A non-volatile universal logic gate and/or memory cell, comprising:
a substrate over which a piezoelectric film is deposited, wherein the substrate is conductive or an additional conducting layer is interposed between the substrate and the piezoelectric film;
a skewed magneto-tunneling junction (MTJ) formed on the piezoelectric film, comprising
a soft magnetic layer consisting of a magnetostrictive nanomagnet in elastic contact with the piezoelectric film, wherein the soft magnetic layer has a magnetization vector with two stable orientations,
a spacer layer, and
a hard magnetic layer permanently magnetized along a direction that subtends a non-zero angle with a magnetization of the soft magnetic layer in an absence of external forces;

a magnetic field source providing a permanent magnetic field; and
at least one pair of electrodes arranged over the piezoelectric film such that a line joining members of the at least one pair of electrodes crosses the soft magnetic layer,
wherein application of a voltage to a pair of electrodes of the at least one pair of electrodes generates electric fields causing a strain in the piezoelectric film, said strain being transferred to the soft magnetic layer,
wherein compressive strain which exceeds a first threshold causes the magnetization vector of the soft magnetic layer to maintain or rotate to one of the two stable orientations, and tensile strain which exceeds a second threshold causes the magnetization vector to maintain or rotate to the other of the two stable orientations,
wherein a resistance of the MTJ is a high state when the magnetization vector of the soft magnetic layer has one of the two stable orientations and a low state when the magnetization vector has the other of the two stable orientations,
wherein either the high state or the low state of the resistance of the MTJ encodes a binary bit of “0” and the other a binary bit of “1”, and
wherein the magnetization vector of the soft magnetic layer maintains a constant orientation in the absence of strain in the piezoelectric film.

7. The non-volatile universal logic gate and/or memory cell of claim 6 , wherein the first and second thresholds are determined by the shape anisotropy, material composition, and processing of the soft magnetic layer; and the magnitude and direction of the permanent magnetic field.

8. The non-volatile universal logic gate and/or memory cell of claim 7 , wherein the non-volatile logic gate and/or memory cell is configured as an NAND gate with the soft magnetic layer having a high shape anisotropy.

9. The non-volatile universal logic gate and/or memory cell of claim 7 , wherein the non-volatile logic gate and/or memory cell is configured as an NOR gate with the soft magnetic layer having a low shape anisotropy.

10. The non-volatile universal logic gate and/or memory of claim 6 , wherein the permanent magnetic field is directed along the hard axis of the soft magnetic layer, the hard axis being a direction of maximal energy instability.

11. The non-volatile universal logic gate and/or memory cell of claim 6 , wherein the line joining the members of the at least one pair of electrodes passes through a center of the soft magnetic layer.

12. The non-volatile universal logic gate and/or memory cell of claim 6 , further comprising
first and second voltage-in lines which, when voltages are applied thereto, determine a magnitude and/or polarity of the voltage applied to the pair of electrodes, said voltage determining whether the magnetization vector of the soft magnetic layer maintains or rotates to a first or a second of the two stable orientations.

13. The non-volatile universal logic gate and/or memory cell of claim 6 , further comprising
a constant current source and bias voltage source which provide for an output voltage indicative of the resistance of the MTJ and hence the encoded binary bit.

14. The non-volatile universal logic gate and/or memory cell of claim 13 , wherein the non-volatile universal logic gate and/or memory cell is configured as an artificial neuron comprising a plural

Assignees

• Univ Virginia Commonwealth

Inventors

• Bandyopadhyay Supriyo
• Atulasimha Jayasimha
• Biswas Ayan Kumar

Classifications

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/22

  using ferroelectric elements · CPC title

• G11C2013/0095

  Write using strain induced by, e.g. piezoelectric, thermal effects · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title