FinFET semiconductor devices including dummy structures

Patent metadata

Field	Value
Publication number	US-9379107-B2
Application number	US-201514693017-A
Country	US
Kind code	B2
Filing date	Apr 22, 2015
Priority date	Apr 22, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first active fin and a second active fin which protrude from a substrate and extend along a first direction;
a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction;
a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction; and
a dummy gate structure which is in a space between the first gate structure and the second gate structure but does not extend on an active fin.

2. The semiconductor device of claim 1 , wherein the first gate structure and the second gate structure are separated by a first distance, and the dummy gate structure is interposed between the first gate structure and the second gate structure.

3. The semiconductor device of claim 2 , wherein the first distance is 30 nm or more.

4. The semiconductor device of claim 1 , wherein a width of the dummy gate structure in the first direction is greater than or equal to a width of the first gate structure in the first direction and is also greater than or equal to a width of the second gate structure in the first direction.

5. The semiconductor device of claim 1 , wherein a height of the dummy gate structure is greater than or equal to a height of the first gate structure and is also greater than or equal to a height of the second gate structure.

6. A semiconductor device comprising:
a first fin-type field effect transistor (FinFET) area which comprises a first active fin extending along a first direction and a first gate structure on the first active fin to extend along a second direction intersecting the first direction;
a second FinFET area which is adjacent to the first FinFET area in the second direction and comprises a second active fin extending along the first direction and a second gate structure on the second active fin to extend along the second direction; and
a dummy gate structure area which overlaps a region of the first FinFET area and a region of the second FinFET area but does not extend on an active fin.

7. The semiconductor device of claim 6 , wherein the region of the first FinFET area comprises a region in which the first gate structure is not formed, and the region of the second FinFET area comprises a region in which the second gate structure is not formed.

8. The semiconductor device of claim 6 , wherein the region of the first FinFET area and the region of the second FinFET area are adjacent to each other.

9. The semiconductor device of claim 6 further comprising a dummy gate structure in the dummy gate structure area.

10. The semiconductor device of claim 9 , wherein a width of the dummy gate structure in the first direction is greater than or equal to a width of the first gate structure in the first direction and is also greater than or equal to a width of the second gate structure in the first direction.

11. The semiconductor device of claim 9 , wherein a height of the dummy gate structure is greater than or equal to a height of the first gate structure and is also greater than or equal to a height of the second gate structure.

12. A semiconductor device comprising:
a first active fin and a second active fin which protrude from a substrate and extend along a first direction;
a first gate structure on the first active fin to extend along a second direction intersecting the first direction;
a second gate structure on the second active fin to extend along the second direction and located adjacent to the first gate structure in the second direction; and
a third gate structure not extending on an active fin and extending along the second direction between the first and second gate structures.

13. The semiconductor device of claim 12 wherein the third gate structure is spaced apart from the first gate structure and the second gate structure.

14. The semiconductor device of claim 12 wherein the third gate structure comprises a first extension of the first gate structure that extends towards the second gate structure along the second direction and a second extension of the second gate structure that extends towards the first gate structure along the second direction.

15. The semiconductor device of claim 14 wherein the first and second extensions are spaced apart from one another along the second direction by less than 30 nm.

16. The semiconductor device of claim 12 wherein the first, second and third gate structures each comprises a first layer, a second layer on the first layer and a third layer on the second layer remote from the first layer and on sidewalls of the first and second layers.

17. The semiconductor device of claim 16 wherein the first layer comprises polysilicon, the second layer comprises a hard mask and the third layer comprises an insulating material.

18. The semiconductor device of claim 1 wherein the first, second and dummy gate structures each comprises a first layer, a second layer on the first layer and a third layer on the second layer remote from the first layer and on sidewalls of the first and second layers.

19. The semiconductor device of claim 9 wherein the first, second and dummy gate structures each comprises a first layer, a second layer on the first layer and a third layer on the second layer remote from the first layer and on sidewalls of the first and second layers.

Assignees

• Lee Bok-Young
• Lee Jeong-Yun
• Kim Dong-Hyun
• Kim Myeong-Cheol
• Han Dong-Woo
• Samsung Electronics Co Ltd

Inventors

• Lee Bok-Young
• Lee Jeong-Yun
• Kim Dong-Hyun
• Kim Myeong-Cheol
• Han Dong-Woo

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0172

  Manufacturing their gate conductors · CPC title