Nonvolatile semiconductor storage device having a charge storage layer that includes metal grains

Patent metadata

Field	Value
Publication number	US-9378962-B2
Application number	US-201213601539-A
Country	US
Kind code	B2
Filing date	Aug 31, 2012
Priority date	Mar 19, 2012
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A nonvolatile semiconductor storage device includes a semiconductor layer, a first insulating film formed on the semiconductor layer, a charge storage layer formed on the first insulating film and having fine metal grains, a second insulating film formed on the charge storage layer, and a gate electrode formed on the second insulating film. During a write operation, a differential voltage is applied across the gate electrode and the semiconductor layer to place the gate electrode at a lower voltage than the semiconductor layer and cause a positive electric charge to be stored in the charge storage layer.

First claim

What is claimed is:

1. A nonvolatile semiconductor storage device comprising:
an n-type semiconductor layer;
a first insulating film formed on the semiconductor layer;
a charge storage layer formed on the first insulating film and having metal grains that are coated with a first organic substance;
a second insulating film formed on the charge storage layer;
a gate electrode formed on the second insulating film;
a molecular layer formed between the first insulating film and the charge storage layer, the molecular layer including a second organic substance different from the first organic substance; and
a p-type source region and a p-type drain region formed in the semiconductor layer on a first side and a second side of the gate electrode, respectively.

2. The nonvolatile semiconductor storage device according to claim 1 , wherein a positive electric charge stored in the charge storage layer indicates a data written state.

3. The nonvolatile semiconductor storage device according to claim 1 , wherein the metal grains are metal nano grains.

4. The nonvolatile semiconductor storage device according to claim 3 , wherein the metal grains are gold nano grains.

5. The nonvolatile semiconductor storage device according to claim 4 , wherein the grain size of the gold nano grains ranges from 0.5 nm to 2 nm.

6. The nonvolatile semiconductor storage device according to claim 1 , wherein, when an erase voltage is applied across the gate electrode and the semiconductor layer to set the gate electrode at a higher voltage relative to the semiconductor layer, an amount of positive electric charge stored in the charge storage layer is reduced.

7. The nonvolatile semiconductor storage device according to claim 1 , wherein, when a read voltage is applied across the source region and the drain region, a current flow between the source region and drain region following application of the read voltage is sensed to determine a written state.

8. The nonvolatile semiconductor storage device according to claim 7 , wherein the current flow that is greater than a threshold indicates the written state.

9. The nonvolatile semiconductor storage device according to claim 7 , wherein the current flow that is less than a threshold indicates a non-written state.

10. The nonvolatile semiconductor storage device according to claim 1 , wherein, when a verify voltage is applied across the source region and the drain region and a current flow between the source region and the drain region is below a threshold, the write voltage is applied to the gate electrode again.

11. The nonvolatile semiconductor storage device according to claim 1 ,
wherein the film thickness of the first insulating film is in the range of 5 nm to 7 nm, and the film thickness of the second insulating film is in the range of 5 nm to 10 nm.

12. The nonvolatile semiconductor storage device according to claim 1 , wherein the metal grains are made of at least one of Au, Ag, Cu, Pt, Pd, W, Ru, Co, and Ni.

13. The nonvolatile semiconductor storage device according to claim 1 , wherein the first organic substance is an alkane thiol.

14. The nonvolatile semiconductor storage device according to claim 1 , wherein, when a write voltage is applied across the gate electrode and the semiconductor layer to cause the gate electrode to be at a negative voltage relative to the semiconductor layer, a positive electric charge is stored in the charge storage layer.

15. The nonvolatile semiconductor storage device according to claim 1 , wherein the molecular layer is a self-assembled molecular monolayer.

16. The nonvolatile semiconductor storage device according to claim 1 , wherein the second organic substance includes a hydrocarbon compound having a thiol group at a first end and a silanol group at a second end.

17. The nonvolatile semiconductor storage device according to claim 1 , wherein the second organic substance includes a molecule represented by following formula, wherein R 3 is one of OCH 3 , OC 2 H 5 , OC 3 H 5 , Cl, Br, or F and each R 3 is either same or different as each other R 3 , and n is an integer in a range of 1 to 20:

18. A nonvolatile semiconductor storage device comprising:
a semiconductor layer of a first conductivity type;
a first insulating film formed on the semiconductor layer;
a charge storage layer formed on the first insulating film and having metal grains that are coated with a first organic substance;
a second insulating film formed on the charge storage layer;
a gate electrode formed on the second insulating film;
a molecular layer formed between the first insulating film and the charge storage layer, the molecular layer including a second organic substance different from the first organic substance; and
a source region of a second conductivity type and a drain region of the second conductivity type, the source region and the drain region being formed in the semiconductor layer on a first side and a second side of the gate electrode, respectively.

Assignees

• Hattori Shigeki
• Yamagiwa Masakazu
• Terai Masaya
• Nishizawa Hideyuki
• Asakawa Koji
• Fukuzumi Yoshiaki
• Toshiba Kk

Inventors

• Hattori Shigeki
• Yamagiwa Masakazu
• Terai Masaya
• Nishizawa Hideyuki
• Asakawa Koji
• Fukuzumi Yoshiaki

Classifications

• H10D30/6893

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D64/035 Primary

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/42332

  Electricity · mapped topic