Methods and apparatus for soft data generation for memory devices based using reference cells

Patent metadata

Field	Value
Publication number	US-9378835-B2
Application number	US-200913063895-A
Country	US
Kind code	B2
Filing date	Sep 30, 2009
Priority date	Sep 30, 2008
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values.

First claim

We claim:

1. A method for generating at least one soft data value in a memory device, comprising:
writing known data to one or more reference cells in said memory device, wherein said memory device comprises a plurality of cells and wherein at least a portion of said plurality of cells are used as said reference cells;
reading one or more of said reference cells at least some of which have the known data written thereto;
obtaining a read statistic for generating said at least one soft data value for soft decoding of data, wherein said read statistic is based on said read one or more reference cells, wherein said read statistic is obtained based on one or more bits read from said one or more reference cells having said known data written thereto as well as one or more bits contained in said known data that were written to said one or more reference cells;
obtaining said at least one soft data value based on said obtained read statistic; and
applying said at least one soft data value to said soft decoding of said data.

2. The method of claim 1 , wherein said soft data value comprises a soft read value that is used to generate one or more log likelihood ratios.

3. The method of claim 1 , wherein said soft data value comprises one or more log likelihood ratios.

4. The method of claim 1 , wherein said read statistic is determined by comparing one or more bits read from said one or more reference cells having the known data written thereto to one or more bits in said known data.

5. The method of claim 1 , wherein said known data comprises one or more of a bit pattern and a symbol pattern written to a plurality of predetermined reference cells.

6. The method of claim 1 , wherein said read statistic is based on a number of erroneous bits relative to a total number of reference bits in said known data.

7. The method of claim 1 , wherein one or more of said read statistic and said soft data value are obtained from a table.

8. The method of claim 1 , wherein one or more of said read statistic and said soft data value are computed as a function of one or more of endurance, number of program/erase cycles, number of read cycles, retention time, temperature, temperature changes, process corner, inter-cell interference impact, location within said memory device, location within a wordline, location within a memory array, and pattern in aggressor cells.

9. The method of claim 1 , wherein said read statistic is obtained for one or more desired locations of a memory array and wherein said writing step comprises writing said known data to said one or more desired locations.

10. The method of claim 9 , wherein said desired locations comprise one or more of a page location, a wordline location, a bitline location and a given bit within a multi-level cell.

11. The method of claim 10 , wherein said given bit within a multi-level cell comprises one or more of a most significant bit (MSB) and a least significant bit (LSB).

12. The method of claim 10 , wherein said known data is written to desired locations corresponding to one or more of said bits within a multi-level cell.

13. The method of claim 9 , wherein said read statistic is based on a number of erroneous bits in said one or more desired locations relative to a total number of considered bits.

14. The method of claim 9 , wherein said read statistic for one or more desired locations is employed to decode data associated with said one or more desired locations.

15. The method of claim 1 , wherein said read statistic is obtained for a given pattern, PATT, in one or more aggressor cells associated with at least one target cell; and wherein said writing step comprises writing said known data to said at least one target cell; and wherein said method further comprises the steps of determining a number of erroneous target bits having said given pattern, PATT, in said one or more aggressor cells; and obtaining said read statistic for said given pattern based on said number of erroneous target bits.

16. The method of claim 15 , further comprising the step of reading said one or more aggressor cells to determine said pattern, PATT.

17. The method of claim 15 , further comprising the step of writing a known pattern to said one or more aggressor cells.

18. The method of claim 15 , wherein said read statistic is based on a number of erroneous target bits relative to a total number of target bits.

19. The method of claim 15 , wherein said read statistic for said given pattern, PATT, is employed to decode data when said one or more associated aggressor cells comprise said pattern, PATT.

20. The method of claim 1 , wherein said read statistic comprises asymmetric read statistics obtained for a plurality of possible values; and wherein said method further comprises the steps of determining a number of erroneous bits having a first value in said known data; determining said number of erroneous bits having a second value in said known data; obtaining a read statistic for said first value based on said number of erroneous bits having said first value; and obtaining a read statistic for said second value based on said number of erroneous bits having said second value.

21. The method of claim 20 , wherein said read statistics are based on said number of erroneous bits having a respective value relative to a total number of reference bits having said respective value.

22. The method of claim 20 , wherein said asymmetric read statistics are employed to decode data having one or more respective values.

23. The method of claim 1 , wherein said soft data value is iteratively provided to said decoder.

24. The method of claim 1 , wherein said reference cells store substantially all possible levels.

25. The method of claim 1 , wherein said reference cells have a periodic pattern.

26. The method of claim 1 , wherein said reference cells are periodically written or read over time.

27. A system for generating at least one soft data value in a memory device, comprising:
a memory; and
at least one processor, coupled to the memory, operative to:
write known data to one or more reference cells in said memory device, wherein said memory device comprises a plurality of cells and wherein at least a portion of said plurality of cells are used as said reference cells;
read one or more of said reference cells at least some of which have said known data written thereto;
determine a read statistic for generating said at least one soft data value for soft decoding of data, wherein said read statistic is based on said read one or more reference cells, wherein said read statistic is determined based on one or more bits read from said one or more reference cells having said known data written thereto as well as one or more bits obtained from said known data that were written to said one or more reference cells; and
determine said at least one soft data value based on said determined read statistic; and
apply said at least one soft data value to said soft decoding of said data.

28. The system of claim 27 , wherein said read statistic is determined by comparing one or more bits read from said one or more reference cells having the known data written thereto to one or more bits in said known data.

29. The system of claim 27 , wherein said known data comprises one or more of a bit pattern and a symbol pattern written to a plurality of predetermined refere

Assignees

• Burger Jr Harley F
• Haratsch Erich F
• Ivkovic Milos
• Krachkovsky Victor
• Miladinovic Nenad
• Vityaev Andrei
• Yen Johnson
• Seagate Technology Llc

Inventors

• Burger Jr Harley F
• Haratsch Erich F
• Ivkovic Milos
• Krachkovsky Victor
• Miladinovic Nenad
• Vityaev Andrei
• Yen Johnson

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title