Stable memory source bias over temperature and method

Patent metadata

Field	Value
Publication number	US-9378805-B2
Application number	US-201213663939-A
Country	US
Kind code	B2
Filing date	Oct 30, 2012
Priority date	Jan 3, 2012
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Random access memory having a plurality of memory cells, each of the plurality of memory cells having a memory element and a first electrical characteristic being variable based, at least in part, on temperature and a bias circuit operatively coupled to at least one of the plurality of memory cells, the bias circuit being configured to generate a bias voltage for the at least one of the plurality of memory cells. The bias circuit has a second electrical characteristic being variable based, at least in part, on temperature. The first electrical characteristic is approximately proportional to the second electrical characteristic over a predetermined range of temperatures, the predetermined range of temperatures being greater than zero. The bias voltage on each of the plurality of memory cells is approximately proportional with variations in the first electrical characteristic over the predetermined range of temperatures.

First claim

What is claimed is:

1. A random access memory, comprising:
a plurality of memory cells, each of said plurality of memory cells having a memory element and a first electrical characteristic being variable based, at least in part, on temperature;
a bias circuit operatively coupled to at least one of said plurality of memory cells, said bias circuit being configured to generate a bias voltage for said at least one of said plurality of memory cells said bias circuit having a second electrical characteristic being variable based, at least in part, on temperature; and
a voltage buffer operatively coupled between said supply bias circuit and said at least one of said plurality of memory cells;
said bias circuit include at least one dummy memory cell to produce a voltage on an input of the voltage buffer;
said first electrical characteristic being proportional to said second electrical characteristic to automatically track proportionally over a predetermined range of temperatures, said predetermined range of temperatures being greater than zero;
said bias circuit being coupled with at least one of said plurality of memory cells so that said bias voltage on each of said plurality of memory cells is proportional with variations in said at least one of said plurality of memory cells over said predetermined range of temperatures.

2. The random access memory of claim 1 wherein said bias circuit is a source bias circuit.

3. The random access memory of claim 2 further comprising a supply bias circuit operatively coupled to said at least one of said plurality of memory cells, said supply bias circuit being configured to generate a bias voltage for at least one of said plurality of memory cells, said supply bias circuit having said second electrical characteristic being variable based, at least in part, on temperature.

4. The random access memory of claim 1 wherein said bias circuit is a supply bias circuit.

5. The random access memory of claim 4 :
wherein said voltage buffer comprises the input and an output configured to supply said bias voltage, said input being coupled to said supply bias circuit and said output being coupled to said at least one of said plurality of memory cells; and
wherein another one of said plurality of memory cells is coupled to said input of said voltage buffer and configured to supply, in combination with said supply bias circuit, an input voltage related to said bias voltage to said input to said voltage buffer.

6. The random access memory of claim 1 , further comprising a plurality of said bias circuits.

7. The random access memory of claim 6 wherein each of said plurality of bias circuits comprise a bias element with said bias element having said second electrical characteristic being variable based, at least in part, on temperature.

8. The random access memory of claim 6 wherein each one of said plurality of bias circuits corresponds to exactly one of said plurality of memory cells.

9. The random access memory of claim 6 wherein said bias element of each of said bias circuits comprise metal oxide semiconductor transistors.

10. The random access memory of claim 9 wherein said bias element of each of said plurality of bias circuits comprise P-channel metal oxide semiconductor transistors.

11. The random access memory of claim 10 wherein said random access memory is operatively coupled to a power source, wherein each memory element of said plurality of memory cells comprises a P-channel metal oxide semiconductor transistor having a body and wherein said body said P-channel metal oxide semiconductor transistor of at least one of said plurality of memory cells is operatively coupled to said power source.

12. The random access memory of claim 11 wherein said random access memory is operatively coupled to a reference ground, wherein each memory element of said plurality of memory cells comprises an N-channel metal oxide semiconductor transistor having a body and wherein said body of said N-channel metal oxide semiconductor transistor of said at least one of said plurality of memory cells is operatively coupled to said reference ground.

13. The random access memory of claim 10 wherein each memory element of said plurality of memory cells comprises a P-channel metal oxide semiconductor transistor having a body and wherein said body of said P-channel metal oxide semiconductor transistor of at least one of said plurality of memory cells is biased by said bias voltage of said bias element.

14. The random access memory of claim 13 wherein said random access memory is operatively coupled to a reference ground, wherein each memory element of said plurality of memory cells comprises an N-channel metal oxide semiconductor transistor having a body and wherein said body of said N-channel metal oxide semiconductor transistor of said at least one of said plurality of memory cells is operatively coupled to said reference ground.

15. The random access memory of claim 9 wherein said bias element of each of said plurality of bias circuits comprise N-channel metal oxide semiconductor transistors.

16. The random access memory of claim 15 wherein said random access memory is operatively coupled to a reference ground, wherein each memory element of said plurality of memory cells comprises an N-channel metal oxide semiconductor transistor having a body and wherein said body of said N-channel metal oxide semiconductor transistor of at least one of said plurality of memory cells is operatively coupled to said reference ground.

17. The random access memory of claim 15 wherein each memory element of said plurality of memory cells comprises an N-channel metal oxide semiconductor transistor having a body and wherein said body of said N-channel metal oxide semiconductor transistors of at least one of said plurality of memory cells is biased by said bias voltage of said bias element.

18. The random access memory of claim 6 wherein each of said plurality of bias circuits comprise a current mirror, said bias element being a component of said current mirror.

19. The random access memory of claim 18 wherein said memory element of each of said plurality of memory cells has a source node and a power node, said bias circuit being operatively coupled between said power node and a power source.

20. The random access memory of claim 19 wherein said bias circuit is a first bias circuit and wherein a second bias circuit is operatively coupled between said source node and a reference node.

21. The random access memory of claim 20 further comprising:
a supply bias voltage buffer operatively coupled between said first bias circuit and said supply node; and
a source bias voltage buffer operatively coupled between said second bias circuit and said source node.

22. The random access memory of claim 18 wherein said memory element of each of said plurality of memory cells has a source node and a power node, said power node being coupled to said power source and said bias circuit being operatively coupled between said source node and said reference node.

23. The random access memory of claim 22 :
wherein said current mirror comprises said bias element and a current element operatively coupled to said bias element;
wherein a current source induces a current through said current element; and
whereby a bias current is induced through said bias element and said memory element is equivalent to said current and whereby said bias voltage on each source node of said plurality of memory

Assignees

• Medtronic Inc

Inventors

• Walsh Kevin K
• Scott Brandon P
• Tyler Larry E

Classifications

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title