Scan driving circuit

Patent metadata

Field	Value
Publication number	US-9378667-B2
Application number	US-201213664661-A
Country	US
Kind code	B2
Filing date	Oct 31, 2012
Priority date	May 29, 2012
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

The present invention relates to a scan driving circuit, which comprises a decoding circuit, a plurality of level-shift driving circuits, and a control circuit. The decoding circuit produces a decoding signal according to a decoding control signal. The plurality of level-shift driving circuits are coupled to the decoding circuit and produce scan signal sequentially according to the decoding signal. The control circuit is coupled to the plurality of level-shift driving circuit. The control circuit produces a first control signal and a second control signal according to the decoding control signal and transmits the first and second control signals to the plurality of level-shift driving circuits for controlling their turning on and off. Accordingly, by means of the control circuit according to the present invention, the circuit area of each level-shift driving circuit can be reduced, and thus the cost can be reduced as well.

First claim

The invention claimed is:

1. A scan driving device, comprising:
a decoding circuit, producing a decoding signal according a decoding control signal;
a plurality of level-shift driving circuits, coupled to said decoding circuit, and producing a scan signal according to said decoding signal; and
a control circuit, coupled to said plurality of level-shift driving circuits, receiving said decoding control signal and said decoding control signal is used to generate a first control signal and a second control signal, and transmitting said first control signal and said second control signal to said plurality of level-shift driving circuits for controlling enabling or cutoff of said plurality of level-shift driving circuits;
wherein said control circuit comprises an enable circuit and a level-shift unit, said enable circuit receives and produces an enable signal according to said decoding control signal, said level-shift unit is coupled to said enable circuit, and shifts a level of said enable signal for producing said first control signal and said second control signal.

2. The scan driving device of claim 1 , wherein said decoding circuit produces said decoding signal according to a least significant bit of said decoding control signal.

3. The scan driving device of claim 1 , wherein said level-shift driving circuit comprises:
a first transistor, having a control for receiving said first control signal, and having a first terminal coupled to a first power terminal;
a second transistor, having a control coupled to a second terminal of said first transistor, having a first terminal coupled to said first power terminal, and having a second terminal coupled to an output of said level-shift driving circuit;
a third transistor, having a control for receiving said decoding signal, having a first terminal coupled to said second terminal of said first transistor and said control of said second transistor, and having a second terminal coupled to a ground;
a fourth transistor, having a control for receiving said decoding signal. and having a first terminal coupled to a second power terminal;
a fifth transistor, having a control coupled to a second terminal of said fourth transistor, having a first terminal coupled to said second terminal of said second transistor and said output, and having a second terminal for receiving a reference voltage;
a sixth transistor, having a control coupled to said output, having a first terminal coupled to said second terminal of said fourth transistor and said control of said fifth transistor; and
a seventh transistor, having a control or receiving said second control signal, having a first terminal coupled to a second terminal of said sixth transistor, and having a second terminal for receiving said reference voltage.

4. The scan driving device of claim 1 , wherein said control circuit further comprises a bias generating circuit, coupled to said level-shift unit, and producing said first control signal according an output signal of said level-shift unit.

5. The scan driving device of claim 4 , wherein said bias generating circuit is a current mirror circuit.

6. The scan driving device of claim 4 , wherein said bias generating circuit comprises:
an impedance device, having a first terminal coupled to said first power terminal;
a current source, having a first terminal coupled to a second terminal of said impedance device, and having a second terminal coupled to said ground;
a first switch, having a first terminal coupled to said second terminal of said impedance device and said first terminal of said current source, having a second terminal coupled to an output of said bias generating circuit, and controlled by said output signal of said level-shift unit; and
a second switch, having a first terminal coupled to said output of said bias generating circuit, having a second terminal coupled to said ground, and controlled by said output signal of said level-shift unit.

7. The scan driving device of claim 1 , wherein said enable circuit comprises:
a delay unit, used for delaying said decoding control signal; and
a logic unit, having a first terminal coupled to said delay unit for receiving said delayed decoding control signal, having a second terminal for receiving said decoding control signal, and producing said enable signal according said decoding control signal and said delayed decoding control signal.

Assignees

• Sitronix Technology Corp

Inventors

• Su Chung-Hsin

Classifications

• G09G3/00 Primary

  Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title