Interrupt return instruction with embedded interrupt service functionality

Patent metadata

Field	Value
Publication number	US-9378164-B2
Application number	US-201113997651-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

First claim

What is claimed is:

1. A processor implemented on a semiconductor chip, comprising:
an execution unit having the following to execute an interrupt handling instruction:
storage circuitry to hold different sets of micro-ops, each set of micro-ops to handle a different interrupt;
first logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is for;
second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt; and
look up table circuitry to provide a pointer to one of said sets in said storage circuitry in response to a problem code for said interrupt being presented to said look up table circuitry.

2. The processor of claim 1 wherein said storage circuitry is a ROM.

3. The processor of claim 1 wherein the set of said sets of micro-ops includes micro-ops to insert virtual and physical page numbers into a translation look-aside buffer.

4. The processor of claim 1 wherein said look up table circuitry includes a ROM.

5. The processor of claim 1 wherein said look up table circuitry is coupled to a register, said register to store said problem code.

6. The processor of claim 1 further comprising a register to store a return pointer address.

7. The processor of claim 6 wherein said register is coupled to said second logic circuitry.

8. A processor implemented on a semiconductor chip, comprising:
an execution unit having the following to execute an instruction:
storage circuitry to hold different sets of micro-ops, each set of micro-ops to handle a different interrupt;
first logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is for;
second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt;
a register to hold input operand information of said instruction supplied by said invoking program, said input operand information specifying an item of data desired by said invoking program, said register coupled to said first logic circuitry; and
look up table circuitry to provide a pointer to one of said sets in said storage circuitry in response to a problem code for said interrupt being presented to said look up table circuitry.

9. The processor of claim 8 wherein said storage circuitry is a ROM.

10. The processor of claim 8 wherein the set of said sets of micro-ops includes micro-ops to insert virtual and physical page numbers into a translation look-aside buffer.

11. The processor of claim 8 wherein said look up table circuitry includes a ROM.

12. The processor of claim 8 wherein said look up table circuitry is coupled to a register, said register to store said problem code.

13. The processor of claim 8 further comprising a register to store a return pointer address.

14. The processor of claim 13 wherein said register is coupled to said second logic circuitry.

15. A method performed by an execution unit of a processor to execute an instruction, said method comprising:
receiving a first input operand, said first input operand specifying a problem encountered by an invoking program;
receiving a second input operand, said second input operand specifying a return pointer address to said invoking program;
receiving a third input operand, said third input operand identifying data desired by said invoking program;
using said first input operand as a look up parameter to identify micro-code to handle said problem;
using a pointer into a storage circuit produced by a look up performed with said look up parameter to fetch said micro-code;
executing said micro-code to handle said problem; and
using said return address pointer to return program flow to said invoking program.

16. The method of claim 15 wherein said storage circuit includes a ROM.

17. The method of claim 16 wherein the micro-code comprises micro-ops to insert virtual and physical page numbers into a translation look-aside buffer.

18. The method of claim 16 wherein said method further comprises said micro-code using said third input operand to identify said data.

19. The method of claim 15 wherein said look up is performed with a first ROM.

20. The method of claim 19 wherein said storage circuit includes a second ROM.

Assignees

• Fang Zhen
• Jiang Xiaowei
• Makineni Srihari
• Illikkal Ramesh G
• Iyer Ravishankar
• Intel Corp

Inventors

• Fang Zhen
• Jiang Xiaowei
• Makineni Srihari
• Illikkal Ramesh G
• Iyer Ravishankar

Classifications

• G06F9/4806

  Task transfer initiation or dispatching · CPC title

• G06F9/327 Primary

  for interrupts · CPC title

• G06F9/3016 Primary

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title