Modification of prefetch depth based on high latency event

Patent metadata

Field	Value
Publication number	US-9378144-B2
Application number	US-201314036284-A
Country	US
Kind code	B2
Filing date	Sep 25, 2013
Priority date	Apr 12, 2013
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A prefetch stream is established in a prefetch unit of a memory controller for a system memory at a lowest level of a volatile memory hierarchy of the data processing system based on a memory access request received from a processor core. The memory controller receives an indication of an upcoming high latency event affecting access to the system memory. In response to the indication, the memory controller temporarily increases a prefetch depth of the prefetch stream with respect to the system memory and issues, to the system memory, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming high latency event.

First claim

What is claimed is:

1. A method of prefetching in a data processing system, the method comprising:
in a prefetch unit in a memory controller for a system memory at a lowest level of a memory hierarchy of the data processing system, establishing a prefetch stream based on a memory access request received by the memory controller from a processor core;
during operation of the memory controller, the memory controller receiving an indication of an upcoming memory refresh cycle of the system memory that will temporarily increase access latency to the system memory; and
in response to the indication of the upcoming memory refresh cycle, the memory controller temporarily increasing a prefetch depth of the prefetch stream with respect to the system memory and issuing, to the system memory, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming memory refresh cycle.

2. The method of claim 1 , wherein the establishing comprises establishing the prefetch stream in response to a prefetch read request of the processor core.

3. The method of claim 2 , wherein the establishing comprises establishing the prefetch stream in response to the prefetch read request only if the prefetch read request is marked by a core prefetch unit as belonging to an extended prefetch stream.

4. The method of claim 1 , and further comprising granting the plurality of prefetch requests higher priority than at least one other prefetch request generated by the memory controller.

5. The method of claim 1 , and further comprising prior to issuing each prefetch request among the plurality of prefetch requests, the memory controller obtaining authority to obtain a copy of a target memory block of that prefetch request via communication on a system fabric of the data processing system.

6. The method of claim 1 , and further comprising:
buffering a plurality of target memory blocks obtained by the plurality of prefetch requests in prefetch buffers in the memory controller; and
servicing a demand read request of the processor core by reference to the prefetch buffers.

7. The method of claim 1 , wherein:
the memory access request is a first memory access request; and
the method further comprises advancing the prefetch stream in response to receipt of a second memory access request that hits in an address region of the prefetch stream.

8. The method of claim 1 , and further comprising:
after temporarily increasing the prefetch depth of the prefetch stream, decreasing the prefetch depth of the prefetch stream.

Assignees

• IBM

Inventors

• Dodson John S
• Dooley Miles R
• Goodman Benjiman L
• Joyner Jody B
• Powell Stephen J
• Retter Eric E
• Stuecheli Jeffrey A

Classifications

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F9/383

  Operand prefetching (cache prefetching G06F12/0862) · CPC title