Method and apparatus to use DRAM as a cache for slow byte-addressible memory for efficient cloud applications
US-12174739-B2 · Dec 24, 2024 · US
US9378143B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9378143-B2 |
| Application number | US-201313788200-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 7, 2013 |
| Priority date | Jun 15, 2012 |
| Publication date | Jun 28, 2016 |
| Grant date | Jun 28, 2016 |
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Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
Opening claim text (preview).
What is claimed is: 1. A method for controlling observability of transactional and non-transactional stores, the method comprising: receiving, by a processing circuit, two or more store instructions, the two or more store instructions initiated within an active transaction and including store data, the active transaction effectively delaying committing stores to memory until successful completion of the active transaction, the two or more store instructions comprising at least one transactional store instruction and at least one non-transactional store instruction; storing the store data in a local storage buffer, the storing causing alterations to the local storage buffer from a first state to a second state; receiving a signal that the active transaction has terminated; and based on determining that the active transaction terminated abnormally such that the active transaction is aborted, for each stored data of the two or more store instructions performing: based on determining that the store data was stored in the local storage buffer by the at least one transactional store instruction during the active transaction, reverting the local storage buffer back to the first state; and based on determining that the stored data was stored in the local storage buffer by the at least one non-transactional store instruction during the active transaction, propagating the second state having the stored data to a shared cache. 2. The method of claim 1 , wherein all storage alterations by all of the two or more store instructions are propagated to the shared cache based on determining that the active transaction terminated normally. 3. The method of claim 1 , wherein the store data is stored in a cache line of a local cache and reverting comprises invalidating the cache line. 4. The method of claim 1 , wherein the store data is stored in a cache line of a local cache and reverting comprises refetching the cache line from the shared cache. 5. The method of claim 1 , wherein the received signal is transmitted from a finite state machine (FSM), the FSM indicating for each of the two or more store instructions a state of the two or more store instructions and a state of the active transaction. 6. The method of claim 5 , wherein the state of the two or more store instructions includes one of: a transactional store instruction state; and a non-transactional store state. 7. The method of claim 5 , wherein the state of the active transaction includes one or more of: a transaction in process state; a transaction end state; and a transaction abort state. 8. The method of claim 6 , wherein the local storage buffer comprises a storage buffer control, the storage buffer control receiving signals from the FSM, the signals comprising indications of the state of the two or more store instructions and the state of the active transaction. 9. The method of claim 8 , wherein the storage buffer control performs the reverting and the propagating based on receiving the signals.
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with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions · CPC title
Transactional memory (G06F9/528 takes precedence) · CPC title
with a shared cache · CPC title
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