Adaptive read error recovery for memory devices

Patent metadata

Field	Value
Publication number	US-9378083-B2
Application number	US-201314096733-A
Country	US
Kind code	B2
Filing date	Dec 4, 2013
Priority date	Dec 4, 2013
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

An error of a solid-state non-volatile memory is detected. It is determined whether a type of the error is a first type of error. A voltage recovery process is bypassed based on whether the error is the first type of error. If it is determined that the error is a catastrophic error, the voltage error recovery process is bypassed. If it is determined that an offset of a threshold voltage is not greater than a predetermined value, the voltage error recovery process is bypassed.

First claim

What is claimed is:

1. A method, comprising:
detecting an error of a solid-state, non-volatile memory;
determining whether a type of the error is a first type of error; and
bypassing a voltage error recovery process based on whether the error is the first type of error.

2. The method of claim 1 , wherein the first type of error is a catastrophic error and bypassing the voltage error recovery process in response to a determination that the type of error is the catastrophic error.

3. The method of claim 1 , wherein the first type of error is a threshold voltage error, and determining whether the type of error is the first type of error comprises:
determining whether an offset of a threshold voltage used to access a memory cell of the solid-state memory is greater than a predetermined value;
if the offset is greater than the predetermined value, initiating the voltage error recovery process that adjusts the threshold voltage used to access the memory cell; and
if the offset is not greater than the predetermined value, bypassing the voltage error recovery process.

4. The method of claim 3 wherein the voltage error recovery process comprises determining a direction of the offset.

5. The method of claim 4 , wherein the voltage error recovery process comprises performing one of a retention loss recovery and an endurance loss recovery based on the direction of the offset.

6. The method of claim 1 , further comprising determining whether the type of error is a second type of error and bypassing the voltage error recovery process based on at least one of whether the error is the first type of error and whether the error is the second type of error.

7. The method of claim 1 , further comprising reading a reference pattern stored in the solid-state, non-volatile memory, wherein determining whether an offset of the voltage threshold is greater than the predetermined value comprises determining whether the offset is greater than the predetermined value using the reference pattern.

8. The method of claim 1 , wherein the memory comprises a multi-level memory cells having at least 2 n voltage levels, each voltage level corresponding to n≧2 data bits and an offset for each voltage level is determined independently of offsets for other voltage levels.

9. The method of claim 1 , wherein bypassing the voltage error recovery process comprises performing an interference cancellation recovery process.

10. The method of claim 1 , wherein bypassing the voltage error recovery process comprises performing a redundant parity recovery.

11. A method, comprising:
detecting an error of a solid-state, non-volatile memory;
determining whether the error is a catastrophic error;
if the error is the catastrophic error, bypassing a voltage error recovery process;
if the error is not the catastrophic error:
determining whether an offset of a threshold voltage used to access the memory cell is greater than a predetermined value;
if the offset is greater than the predetermined value, initiating a voltage error recovery process that adjusts the threshold voltage used to access the memory cell; and
if the offset is not greater than the predetermined value, bypassing the voltage error recovery process.

12. The method of claim 11 , wherein if the error is the catastrophic error, bypassing the voltage error recovery process comprises and performing a redundant parity recovery.

13. The method of claim 11 , wherein if the offset is not greater than the predetermined value, bypassing the voltage error recovery process and performing an interference cancellation recovery process.

14. An apparatus comprising:
a controller capable of being coupled to a solid-state, non-volatile memory, the controller configured to perform:
determining whether a type of the error is a first type of error; and
bypassing a voltage error recovery process based on whether the error is the first type of error.

15. The apparatus of claim 14 , wherein the first type of error is the catastrophic error and the controller is configured to bypass the voltage error recovery process in response to a determination that the type of error is the catastrophic error.

16. The apparatus of claim 14 , wherein the first type of error is a threshold voltage error, and the controller is configured to determine whether the type of error is the first type of error by:
determining whether an offset of a threshold voltage used to access a memory cell of the solid-state memory is greater than a predetermined value;
if the offset is greater than the predetermined value, initiating a voltage error recovery process that adjusts the threshold voltage used to access the memory cell; and
if the offset is not greater than the predetermined value, bypassing the voltage error recovery process.

17. The apparatus of claim 16 , wherein the controller is configured to determine a direction of the offset.

18. The apparatus of claim 14 , wherein the controller is configured to determine whether the type of error is a second type of error and bypassing a voltage error recovery process based on at least one of whether the error is the first type of error and whether the error is the second type of error.

19. The apparatus of claim 14 , wherein the controller is configured to:
read a reference pattern stored in the solid-state, non-volatile memory; and
determine whether an offset is greater than the predetermined value using the reference pattern.

20. The apparatus of claim 14 , wherein the memory comprises multi-level memory cells having at least 2 n voltage levels, each voltage level corresponding to n≧2 data bits and an offset for each voltage level is determined independently of offsets for other voltage levels.

Assignees

• Seagate Technology Llc

Inventors

• Ghaly Mai A
• Patapoutian Ara

Classifications

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title