System for display images

Patent metadata

Field	Value
Publication number	US-9377654-B2
Application number	US-201514875031-A
Country	US
Kind code	B2
Filing date	Oct 5, 2015
Priority date	Jun 29, 2011
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A system for displaying images including a display panel is provided. The display panel has a display area and a peripheral area. The display panel includes a metal layer disposed on a first substrate. A second substrate is disposed opposite to the first substrate. A seal is disposed at the peripheral area and between the first and the second substrates and at the peripheral area. A patterned planarization layer is disposed on the first substrate. A passivation layer disposed between the seal and the first substrate, wherein the seal is in contact with a sidewall of the passivation layer.

First claim

What is claimed is:

1. A system for displaying images, including a display panel, having a display area and a peripheral area out of the display area, wherein the display panel comprises:
a first substrate;
a second substrate disposed opposite to the first substrate;
a seal disposed between the first substrate and the second substrate and disposed at the peripheral area;
a patterned planarization layer disposed on the first substrate; and
a passivation layer disposed between the seal and the first substrate;
wherein the seal is in contact with a sidewall of the passivation layer.

2. The system as claimed in claim 1 , wherein the patterned planarization layer comprises at least one opening, and an area of the opening of the patterned planarization layer is 5% to 100% of an area of the seal.

3. The system as claimed in claim 1 , wherein the passivation layer covers a sidewall of the patterned planarization layer to form the sidewall of the passivation layer.

4. The system as claimed in claim 2 , wherein the opening of the patterned planarization layer comprises a plurality of holes.

5. The system as claimed in claim 4 , wherein the plurality of holes are disposed at corners of the peripheral area of the display panel.

6. The system as claimed in claim 1 , wherein the material of the passivation layer comprises silicon nitride or silicon oxide.

7. The system as claimed in claim 1 , further comprising an insulating layer disposed between the passivation layer and the first substrate, wherein a portion of the insulating layer is disposed in at least one opening of the patterned planarization layer.

8. The system as claimed in claim 7 , wherein the material of the patterned planarization layer comprises an organic photoresist and the material of the insulating layer comprises silicon nitride or silicon oxide.

9. The system as claimed in claim 1 , further comprising a metal layer disposed between the passivation layer and the first substrate, wherein the passivation layer covers a sidewall of the metal layer to form the sidewall of the passivation layer.

10. The system as claimed in claim 1 , wherein the sidewall of the passivation layer is not parallel to a surface of the first substrate, wherein the surface of the first substrate is opposite to the second substrate.

11. An electronic device, comprising:
a display, including a display panel having a display area and a peripheral area out of the display area, wherein the display panel comprises:
a first substrate;
a second substrate disposed opposite to the first substrate;
a seal disposed between the first substrate and the second substrate and disposed at the peripheral area;
a patterned planarization layer disposed on the first substrate; and
a passivation layer disposed between the seal and the first substrate;
wherein the seal is in contact with a sidewall of the passivation layer; and
a control unit coupled to the display to provide an input data to the display such that the display displays images.

12. The electronic device as claimed in claim 11 , further comprising a metal layer disposed between the passivation layer and the first substrate, wherein the passivation layer covers a sidewall of the metal layer to form the sidewall of the passivation layer.

13. The electronic device as claimed in claim 11 , wherein the patterned planarization layer comprises at least one opening, and an area of the opening of the patterned planarization layer is 5% to 100% of an area of the seal.

14. The electronic device as claimed in claim 13 , wherein the opening of the patterned planarization layer comprises a plurality of holes.

15. The electronic device as claimed in claim 14 , wherein the plurality of holes are disposed at corners of the peripheral area of the display panel.

16. The electronic device as claimed in claim 11 , wherein the passivation layer covers a sidewall of the patterned planarization layer to form the sidewall of the passivation layer.

17. The electronic device as claimed in claim 11 , wherein the material of the passivation layer comprises silicon nitride or silicon oxide.

18. The electronic device as claimed in claim 11 , further comprising an insulating layer disposed between the passivation layer and the first substrate, wherein a portion of the insulating layer is disposed in at least one opening of the patterned planarization layer.

19. The electronic device as claimed in claim 18 , wherein the material of the patterned planarization layer comprises an organic photoresist and the material of the insulating layer comprises silicon nitride or silicon oxide.

20. The electronic device as claimed in claim 11 , wherein the sidewall of the passivation layer is not parallel to a surface of the first substrate, wherein the surface of the first substrate is opposite to the second substrate.

Assignees

• Innocom Tech Shenzhen Co Ltd
• Innolux Corp

Inventors

• Wang Chun-Ming
• Sung Hsixg-Ju
• Lee Te-Yu

Classifications

• G02F1/1339 Primary

  Gaskets; Spacers; Sealing of cells · CPC title

• G02F2001/133357

  Physics · mapped topic

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G02F1/13306

  Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence) · CPC title

• G02F1/1341

  Filling or closing of cells · CPC title