Mode estimation in pipelined architectures

Patent metadata

Field	Value
Publication number	US-9374592-B2
Application number	US-201213607716-A
Country	US
Kind code	B2
Filing date	Sep 8, 2012
Priority date	Sep 8, 2012
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A video system includes an encoder for generating a compressed bit stream in response to a received video signal. The encoder includes a mode decision processor that is arranged to determine whether the mode of a first pixel block in a first row is an “intra-mode” or an “inter-mode.” The encoder also includes a mode estimation processor that is arranged to estimate the mode of a left pixel block in a second row that is received after the first row in response to the determined mode of the first pixel block in the first row. The encoder also includes a pixel block processor that is arranged to process a pixel block in the second row that is to the right of the left pixel block in response to the estimated mode of the left pixel block.

First claim

What is claimed is:

1. A video processor, comprising
a mode decision processor that is arranged to determine whether the mode of a first pixel block in a first row is an “intra-mode” or an “inter-mode;”
a mode estimation processor that is arranged to estimate whether the mode of a left pixel block in a second row that is received after the first row in response to the determined mode of the first pixel block in the first row is more likely an “intra-mode” or an “inter-mode”, wherein the left pixel block neighbors the first pixel block in the first row; and
a pixel block processor that is arranged to process a pixel block in the second row that is to the right of the left pixel block in response to the estimated more likely “intra-mode” or “inter-mode” of the left pixel block.

2. The processor of claim 1 , wherein the mode decision processor is arranged to provide an indication of which intra-prediction directions are allowed when operating in a constrained intra-prediction mode.

3. The processor of claim 1 , wherein the pixel blocks are generated in response to a received video signal containing frames.

4. The processor of claim 1 , wherein the received pixel blocks are arranged in accordance with a spatial arrangement in the frame.

5. The processor of claim 4 , wherein the received pixel blocks are received in a raster order in accordance with the spatial arrangement in the frame.

6. The processor of claim 1 , wherein the mode estimation processor is arranged in a pipeline processor where the output of the mode estimation processor is coupled to the input of the pixel block processor.

7. The processor of claim 6 , wherein the mode decision processor is arranged in a pipeline processor where the output of the pixel block processor is coupled to the input of the mode decision processor.

8. The processor of claim 7 , wherein the left pixel block in a second row is processed by the mode decision processor while the pixel block in the second row that is to the right of the left pixel block is processed by the mode estimation processor.

9. The processor of claim 1 , wherein the mode estimation processor is arranged to estimate the mode of the left pixel block in response to a determined mode of the pixel block to the left of the first pixel block in the first row and in response to a determined mode of the pixel block to the right of the first pixel block in the first row.

10. The processor of claim 9 , wherein the mode estimation processor is arranged to estimate the mode of the left pixel block in response to numeric values that represent the determined modes of the pixel block to the left of the first pixel block in the first row, the first pixel block in the first row, and the determined mode of the pixel block to the right of the first pixel block in the first row.

11. The processor of claim 1 , wherein the estimated mode of the left pixel block is used to process the pixel block in the second row that is to the right of the left pixel block before the determination for the mode of the left macro block is made.

12. A video system, comprising:
a video processor that is arranged to receive a video signal from which rows of pixel blocks are determined; and
an encoder that is arranged to determine whether the mode of a first pixel block in a first row is an “intra-mode” or an “inter-mode,” that is arranged to estimate whether the mode of a left pixel block in a second row that is received after the first row in response to the determined mode of the first pixel block in the first row is more likely an “intra-mode” or an “inter-mode”, wherein the left pixel block neighbors the first pixel block in the first row; and that is arranged to process a pixel block in the second row that is to the right of the left pixel block in response to the estimated more likely “intra-mode” or “inter-mode” of the left pixel block.

13. The system of claim 12 , wherein the encoder is arranged to estimate a mode for each left pixel block having a pixel block arranged to the right of the left pixel block in the second row.

14. The system of claim 12 , wherein the mode of the left pixel block in the second row is estimated in response to a determined mode of one or more neighboring pixel blocks in a row that is received before the second row.

15. The system of claim 12 , wherein the mode of the left pixel block in the second row is estimated in response to a determined mode of one or more neighboring pixel blocks in a row that is received before the second row.

16. A method for video processing, comprising:
determining whether the mode of a first pixel block in a first row is an “intra-mode” or an “inter-mode;”
estimating the mode of a left pixel block in a second row that is received after the first row in response to the determined mode of the first pixel block in the first row is more likely “intra-mode” or “inter-mode”, wherein the left pixel block neighbors the first pixel block in the first row; and
processing a pixel block in the second row that is to the right of the left pixel block in response to the estimated more likely “intra-mode” or “inter-mode” of the left pixel block.

17. The method of claim 16 , comprising performing the method of claim 16 for each pixel block in the second row that has a pixel block to the left.

18. The method of claim 17 , comprising encoding a video stream in response to the estimated more likely “intra-mode” or “inter-mode” of the left pixel block.

19. The method of claim 16 , wherein the mode of the left pixel block in the second row is estimated in response to a determined mode of one or more neighboring pixel blocks in a row that is received before the second row.

20. The method of claim 19 , wherein the neighboring pixel blocks in the row that is received before the first row have a directly or diagonally adjacent to the left pixel block in the second row.

Assignees

• Mathew Manu
• Srinivasan Ranga Ramanujam
• Texas Instruments Inc

Inventors

• Mathew Manu
• Srinivasan Ranga Ramanujam

Classifications

• H04N19/11

  among a plurality of spatial predictive coding modes · CPC title

• H04N19/107

  between spatial and temporal predictive coding, e.g. picture refresh · CPC title

• H04N19/176

  the region being a block, e.g. a macroblock · CPC title

• H04N19/42 Primary

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title