Method, apparatus, and system for measurement of noise statistics and bit error ratio estimation

Patent metadata

Field	Value
Publication number	US-9374202-B2
Application number	US-201313842320-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ratio determined for a device.

First claim

What is claimed is:

1. An apparatus comprising:
a first slicer element to:
receive a sample voltage from a device;
determine a first binary value corresponding to the sample voltage;

a second slicer element to:
receive the sample voltage;
determine a second binary value corresponding to the sample voltage, wherein the second binary value is to be determined based on a comparison of the sample voltage with a reference voltage of the second slicer element; and

logic to:
compare the first binary value and the second binary value; and
generate a particular output to indicate that the first and second binary values do not match, wherein the output is to indicate a soft error associated with the sample voltage and is to be used in determining a soft error ratio for a signal, and the signal comprises the sample voltage.

2. The apparatus of claim 1 , wherein the reference voltage comprises an adjustable reference voltage.

3. The apparatus of claim 2 , wherein the second slicer element is to:
adjust the reference voltage to a different reference voltage;
determine a different value corresponding to the sample voltage based on a comparison of the sample voltage with the different reference voltage.

4. The apparatus of claim 1 , wherein the logic is further to determine whether the reference voltage is positive or negative.

5. The apparatus of claim 1 , wherein the second binary value is to be a “1” if the sample voltage is greater than the reference voltage and a “0” if the sample voltage is less than the reference voltage.

6. The apparatus of claim 1 , wherein the sample voltage is one of a series of sample voltages included in the signal, the first slicer element is to determine values for each of the sample voltages, the second slicer element is to determine values for each of the sample values, and the logic is to compare corresponding values determined by each of the first and second slicer elements to calculate the soft error ratio.

7. The apparatus of claim 6 , wherein the logic is to determine a threshold number of candidate bits and generate the soft error ratio in response to detecting a number of candidate bits equal or greater than the threshold number of candidate bits.

8. The apparatus of claim 6 , wherein the logic is to determine a threshold number of soft errors and generate the soft error ratio in response to detecting a number of soft errors equal or greater than the threshold number of soft errors.

9. The apparatus of claim 6 , wherein the logic is to determine a threshold number of candidate bits and a threshold number of soft errors and generate the soft error ratio in response to the earlier of detecting a number of soft errors equal or greater than the threshold number of soft errors and detecting a number of candidate bits equal or greater than the threshold number of candidate bits.

10. The apparatus of claim 6 , wherein the soft error rate is calculated for the reference voltage by dividing a number of detected soft errors by twice a number of detected candidate bits.

11. The apparatus of claim 10 , wherein each candidate bit represents a “1” value determined by the first slicer element from the series of sample voltages.

12. The apparatus of claim 6 , wherein the logic is to determine a plurality of soft error ratios for each of a range of reference voltages.

13. The apparatus of claim 12 , wherein the logic is to determine a cumulative probability function for a receiver from the plurality of soft error ratios.

14. The apparatus of claim 12 , wherein the signal is to be sent during live operation of a link.

15. A method comprising:
receiving a sample voltage from a device at a first slicer element and a second slicer element;
identifying a decision by the first slicer element based on the sample voltage;
comparing the decision of the first slicer element with a decision of the second slicer element based on the sample voltage, wherein the decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element and the decision of the first slicer element comprises a first binary value and the decision of the second slicer element comprises a second binary value;
determining a soft error associated with the sample voltage when the first binary value does not match the second binary value; and
determining a soft error rate for a signal comprising the sample voltage based on the soft error.

16. The method of claim 15 , further comprising adjusting the reference voltage to a different reference voltage.

17. The method of claim 16 , further comprising:
receiving a second sample voltage at the first and second slicer elements;
identifying a second decision by the first slicer element based on the second sample voltage; and
comparing the second decision of the first slicer element with a second decision of the second slicer element based on the second sample voltage, wherein the second decision of the second slicer element is to be generated from a comparison of the second sample voltage with the different reference voltage.

18. The method of claim 15 , wherein the second binary value corresponding to the decision of the second slicer is to be a “1” if the sample voltage is greater than the reference voltage and a “0” if the sample voltage is less than the reference voltage.

19. The method of claim 15 , wherein the sample voltage is one of a plurality of sample values in a signal received from the device, the method further comprising determining a number of soft errors corresponding to the plurality of sample values.

20. The method of claim 19 , further comprising determining a soft error ratio corresponding to the reference voltage based on the number of soft errors.

21. The method of claim 20 , further comprising determining a corresponding soft error ratio for each of a plurality of reference voltages of the second slicer element.

22. The method of claim 21 , further comprising determining a cumulative probability function for a receiver from the plurality of soft error ratios.

23. The method of claim 20 , further comprising determining a number of candidate bits in the plurality of sample values.

24. The method of claim 23 , further comprising determining the soft error rate for the reference voltage by dividing the number of soft errors by twice the number of candidate bits.

25. The method of claim 15 , wherein the first binary value corresponding to the decision of the first slicer element is to be a “1” if the sample voltage is greater than a reference voltage of the first slicer element and a “0” if the sample voltage is less than the reference voltage of the first slicer element.

26. The method of claim 25 , wherein the reference voltage of the first slicer element is approximately zero.

27. At least one non-transitory machine accessible storage medium having instructions stored thereon, the instructions when executed on a machine, cause the machine to:
identify a decision by a first slicer element based on a sample voltage, wherein the sample voltage is sampled by both the first slicer element and a second slicer element;
compare the decision of the first slicer element with a decision of the second slicer element based on the sample voltage, wherein the decision of the second slicer element is to be generated from a comparison of the sample voltage with

Assignees

• Intel Corp

Inventors

• Ran Adee O
• Mezer Amir
• Gazinski Ophir
• Ravi Sanjay R
• Ellis David G
• Peters Stephen J
• Shuey Jeffrey M

Classifications

• H04L1/203 Primary

  Details of error rate determination, e.g. BER, FER or WER · CPC title