Multi-bit cell attenuator

US9374078B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9374078-B2
Application numberUS-201213539409-A
CountryUS
Kind codeB2
Filing dateJun 30, 2012
Priority dateJun 30, 2012
Publication dateJun 21, 2016
Grant dateJun 21, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

First claim

Opening claim text (preview).

What is claimed: 1. A device comprising: a step attenuator having a range of attenuation levels and comprising a first cell, where a cell is selectable to provide one or more cell attenuation levels; the first cell comprising: a plurality of first attenuation arms between node set A; and a plurality of second attenuation arms between node set B, where node set A and node set B are different, and where each of the plurality of first attenuation arms and each of the plurality of second attenuation arms are selectable to enable or disable them independently in the step attenuator in a plurality of different combinations comprising at least one of the plurality of first attenuation arms and at least one of the plurality of second attenuation arms to provide a plurality of first cell attenuation levels, wherein the first cell is configured for hybrid intra cell operation or in combination with at least one other cell for hybrid inter cell operation that reduces binary operated glitches and thermometer operated insertion loss in the intra cell or inter cell operation. 2. The device of claim 1 , wherein the plurality of first attenuation arms comprises a plurality of bridge arms and the plurality of second attenuation arms comprises a plurality of shunt arms in a variable bridged tee attenuator. 3. The device of claim 2 , wherein the plurality of first attenuation arms are configured in parallel between node set A and the plurality of second attenuation arms are configured in parallel between node set B. 4. The device of claim 3 , wherein the attenuation level is stepped by decreasingly combining arms in the plurality of the first attenuation arms and increasingly combining arms in the plurality of second attenuation arms or vice versa. 5. The device of claim 1 , the first cell further comprising: a bypass attenuation arm, where the first cell is selectable to bypass attenuation by the first cell by selecting the bypass attenuation arm. 6. The device of claim 5 , the step attenuator comprising a plurality of cells, the plurality of cells comprising a second cell where the first cell is configured to receive a signal before the second cell, wherein the first cell is configured to handle a higher signal power or a higher signal level than the second cell. 7. The device of claim 6 , wherein the first cell is configured to handle the higher signal power or the higher signal level by stacking transistors in one or more of the first attenuation arm, the second attenuation arm, the bypass attenuation arm or other arm. 8. The device of claim 1 , wherein the plurality of first attenuation arms comprises a plurality of series arms and the plurality of second attenuation arms comprises a plurality of shunt arms in a variable tee, bridged tee or pi attenuator. 9. The device of claim 1 , the step attenuator comprising a plurality of cells, wherein the plurality of cells comprise a hybrid of fixed and variable attenuation level cells. 10. The device of claim 1 , wherein each attenuation step between each of the plurality of first cell attenuation levels is the same. 11. The device of claim 1 , the step attenuator comprising a plurality of cells, the plurality of cells comprising a third cell, wherein an intra-cell coding of the third cell is different than an intra-cell coding of the first cell. 12. The device of claim 1 , the step attenuator comprising a plurality of cells, wherein an intra-cell coding of the first cell is different from an inter-cell coding of the plurality of cells. 13. The device of claim 1 , wherein each selectable arm comprises at least one fixed impedance selectable by at least one control signal applied to at least one transistor. 14. A device comprising: a step device having a plurality of cells, each cell being selectable to provide one or more of a plurality of selectable steps for the step device, where at least one of the plurality of cells, a first cell, is a variable cell selectable to provide a plurality of the plurality of selectable steps over a cell range at a cell resolution that reduce glitches equivalent to binary coded glitches and reduce thermometer coded insertion loss in the operation of the first cell. 15. The device of claim 14 , wherein the step device is hybrid-coded or hybrid-codable. 16. The device of claim 14 , the plurality of cells comprising a hybrid of fixed and variable step value cells, the step device further comprising: a second cell of the plurality of cells, the second cell comprising a fixed cell selectable to provide only one of the plurality of selectable steps. 17. The device of claim 14 , the step device comprising a plurality of variable cells, wherein at least one of the cell range and the cell resolution of the first cell is different from a cell range and a cell resolution of another variable cell, a third cell. 18. The device of claim 14 , the step device comprising a plurality of variable cells, wherein an intra-cell coding of the first cell is different than an intra-cell coding of another variable cell. 19. A device comprising: a hybrid coded or hybrid codable step device having a plurality of selectable steps that reduce glitches equivalent to binary coded glitches and reduce thermometer coded insertion loss in the operation of the hybrid coded or hybrid codable step device. 20. The device of claim 19 , further comprising: a variable cell with variable cell resolution selectable to provide a plurality of the plurality of selectable steps with nonuniform resolution.

Assignees

Inventors

Classifications

  • using resistors · CPC title

  • by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title

  • Attenuating devices (dissipative terminating devices H01P1/26) · CPC title

  • Resistor networks not otherwise provided for · CPC title

  • H03M1/68Primary

    with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

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What does patent US9374078B2 cover?
Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, inser…
Who is the assignee on this patent?
Bawell Shawn, Mourant Jean-Marc, Huang Feng-Jung, and 1 more
What technology area does this patent fall under?
Primary CPC classification H03M1/68. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 21 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).