Post fabrication tuning of an integrated circuit

Patent metadata

Field	Value
Publication number	US-9374072-B2
Application number	US-201414268336-A
Country	US
Kind code	B2
Filing date	May 2, 2014
Priority date	Dec 6, 2012
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

An integrated circuit 2 includes a transistor 26 which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

First claim

We claim:

1. An integrated circuit comprising:
at least one transistor having a plurality of electrical connections and a normal performance characteristic controlled by one or more physical properties of said transistor, said normal performance characteristic arising during normal operations of said transistor that apply normal electrical signals within respective normal ranges to at least some of said plurality of electrical connections of said transistor, said normal performance characteristic having a value resulting in incorrect operation of said integrated circuit upon normal switching of said transistor; and
a tuner configured to apply during a tuning operation a tuning stimulus to a gate of said transistor to permanently change at least one of said one or more physical properties of said transistor that control said normal performance characteristic such that upon resuming modified normal operations with said normal electrical signals said transistor operates with a changed normal performance characteristic, said changed normal performance characteristic having a value resulting in correct operation of said integrated circuit upon normal switching of said transistor.

2. An integrated circuit as claimed in claims 1 , wherein said one or more physical properties of said transistor comprise a switching threshold voltage of said transistor.

3. An integrated circuit as claimed in claim 1 , wherein said normal performance characteristic comprises switching speed of said transistor.

4. An integrated circuit as claimed in claim 1 , wherein said normal performance characteristic comprises gate capacitance of said transistor.

5. An integrated circuit as claimed in claim 1 , wherein said tuner applies a tuning electrical signal having at least one of:
a current level outside said corresponding one of said normal ranges; and
a duration outside said corresponding one of said normal ranges.

6. An integrated circuit as claimed in claim 1 , wherein said transistor has a drain connection and said tuner applies tuning electrical signal to said drain connection.

7. An integrated circuit as claimed in claim 6 , wherein said performance characteristic is switching speed and said switching speed is increased by said application of said tuning electrical signal.

8. An integrated circuit as claimed in claim 1 , wherein said transistor has a back bias connection and said tuner applies a tuning electrical signal to said back bias connection.

9. An integrated circuit as claimed in claim 1 , wherein said integrated circuit includes a memory having a sense amplifier and said transistor is a current source transistor configured to control a slew rate of said sense amplifier.

10. An integrated circuit as claimed in claim 3 , wherein said integrated circuit includes a delay line configured to generate a control signal with a delay timing and said transistor is part of said delay line such that changing said switching speed of said transistor changes said delay timing.

11. An integrated circuit as claimed in claim 3 , wherein said integrated circuit includes a transistor stack configured to generate an output signal pulled up to a first voltage level or pulled down to a second voltage level in dependence upon an input signal and said transistor is part of said transistor stack such that changing said switching speed of said transistor changes at least one of a speed at which said output signal is pulled up or pulled down.

12. An integrated circuit as claimed in claim 3 , wherein said integrated circuit includes a signal path susceptible to a race condition error and said transistor is part of said signal path such that slowing switching of said transistor suppresses occurrence of said race condition.

13. An integrated circuit as claimed in claim 1 , wherein said tuner includes a multiplexer coupled to said at least one of said plurality of connections and configured to supply a tuning electrical signal thereto during said tuning operation and to apply a corresponding normal electrical signal thereto during said normal operation.

14. An integrated circuit as claimed in claim 13 , wherein said tuning electrical signal is applied via a dedicated signal path.

15. An integrated circuit as claimed in claim 4 , wherein said transistor is configured to serve as a capacitor and is switched between a charging state and a discharging state.

16. An integrated circuit as claimed in claim 15 , wherein a magnitude of charge stored by said capacitor in said charging state is dependent upon said gate capacitance of said transistor and said tuner is configured to change said gate capacitance.

17. An integrated circuit as claimed in claim 15 , comprising a memory bit cell and wherein said capacitor is configured to provide a write-assist voltage during a write operation to said memory bit cell.

18. An integrated circuit as claimed in claim 15 , wherein said tuner changes said gate capacitance of said transistor so as to change a magnitude of said write-assist voltage.

19. An integrated circuit as claimed in claim 4 , wherein
said transistor has a gate connection, a source connection and a drain connection,
said transistor is configured to serve as a capacitor having a first connection and a second connection,
said gate connection provides said first connection of said capacitor,
said drain connection and said source connection are connected together and provide said second connection,
said normal switching operation comprises switching between applying a first bias between said first connection and said second connection to charge said capacitor and applying a second bias between said first connection and said second connection to discharge said capacitor, and
said first bias is a reverse bias and said second bias is substantially zero bias.

20. An integrated circuit comprising:
at least one transistor means for performing a switching operation, said transistor means having a plurality of electrical connections and a normal performance characteristic controlled by one or more physical properties of said transistor means, said normal performance characteristic arising during normal operations of said transistor means that apply normal electrical signals within respective normal ranges to at least some of said plurality of electrical connections of said transistor means, said normal performance characteristic having a value resulting in incorrect operation of said integrated circuit upon normal switching of said transistor means; and
tuner means for applying during a tuning operation a tuning stimulus to a gate of said transistor means to permanently change at least one of said one or more physical properties of said transistor means that control said normal performance characteristic such that upon resuming modified normal operations with said normal electrical signals said transistor means operates with a changed normal performance characteristic, said tuner means being coupled to said transistor means, and said changed normal performance characteristic having a value resulting in correct operation of said integrated circuit upon normal switching of said transistor means.

21. A method of tuning operation of an integrated circuit including at least one transistor having a plurality of electrical connections and a normal performance characteristic controlled by one or more physical properties of said transistor, said normal performance characteristic arising during normal operations of said transistor that apply normal electrical signals with

Assignees

• Advanced Risc Mach Ltd

Inventors

• Hold Betina
• Cline Brian
• Lattimore George

Classifications

• H03K5/133 Primary

  using a chain of active delay devices · CPC title