Stress-inducing structures, methods, and materials

Patent metadata

Field	Value
Publication number	US-9373717-B2
Application number	US-201414565243-A
Country	US
Kind code	B2
Filing date	Dec 9, 2014
Priority date	May 19, 2008
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

First claim

What is claimed is:

1. An isolation structure comprising:
a trench disposed in a workpiece;
a first insulating material disposed in a lower portion of the trench;
a stress-inducing material disposed over the first insulating material; and
a divot comprising a gutter-shaped depression disposed in the stress-inducing material.

2. The isolation structure according to claim 1 , wherein the first insulating material comprises a top surface, wherein the stress-inducing material is thicker at a central region of the top surface than at edge regions of the top surface.

3. The isolation structure according to claim 1 , wherein the first insulating material comprises silicon dioxide or a tetra ethyl oxysilane (TEOS)-based oxide.

4. The isolation structure according to claim 1 , wherein the stress-inducing material comprises Si 3 N 4 or Bis-tertiarybutylamino-silane (BTBAS)-based silicon nitride.

5. The isolation structure according to claim 1 , wherein the stress-inducing material comprises ZrO 2 or Zr 2 O 3 .

6. The isolation structure according to claim 5 , wherein the stress-inducing material further comprises CaO, MgO, Er 2 O 3 , Y 2 O 3 , Sm 2 O 3 , Tb 2 O 3 , or another rare earth element-containing material.

7. The isolation structure according to claim 5 , wherein the stress-inducing material further comprise a stress-altering component, and wherein the stress-altering component comprises about 5% or less of the stress-inducing material.

8. The isolation structure according to claim 5 , wherein the stress-inducing material further comprise a stress-altering component, and wherein the stress-altering component comprises about 1% to about 2% of the stress-inducing material.

9. The isolation structure according to claim 1 , wherein the stress-inducing material comprises TiO 2 or Al 2 O 3 .

10. The isolation structure according to claim 1 , wherein the first insulating material comprises a substantially flat top surface.

11. The isolation structure according to claim 1 , wherein the first insulating material comprises a top surface wherein a central region of the top surface comprises a lower height than edge regions of the top surface.

12. The isolation structure according to claim 1 , further comprising a liner disposed between the workpiece and the first insulating material.

13. An isolation structure comprising:
a trench in a substrate;
an insulating material disposed in a majority of the trench;
at a top surface of the insulating material, a first gutter shaped depression disposed in the insulating material;
a stress-inducing material disposed directly on the insulating material and filling the first gutter shaped depression; and
at a top surface of the stress-inducing material, a second gutter shaped depression disposed in the stress-inducing material.

14. The isolation structure according to claim 13 , further comprising a liner between the substrate and the insulating material.

15. The isolation structure according to claim 13 , wherein the stress-inducing material is thicker at a central region of the top surface than at edge regions of the top surface.

16. The isolation structure according to claim 13 , wherein the insulating material comprises oxide, and wherein the stress-inducing material comprises silicon nitride.

17. A transistor comprising:
a gate dielectric layer disposed on a substrate;
a first source/drain disposed in the substrate;
a second source/drain disposed in the substrate;
a gate disposed on the gate dielectric layer between the first source/drain and the second source/drain;
a trench disposed in the substrate;
a first insulating material disposed in a lower portion of the trench;
a stress-inducing material disposed over the first insulating material, wherein the first insulating material comprises a top surface, and wherein the stress-inducing material is thicker at a central region of the top surface than at edge regions of the top surface; and
a divot disposed in the stress-inducing material.

18. The transistor of claim 17 , wherein the trench intersects the gate along one or more sides of the transistor at an intersection, and wherein the divot comprises a portion underlying the gate and filled with gate material at the intersection.

19. The transistor of claim 17 , further comprising a depression disposed in the first insulating material and filled with the stress-inducing material.

20. The transistor of claim 17 , wherein the first insulating material comprises oxide, and wherein the stress-inducing material comprises silicon nitride.

Assignees

• Infineon Technologies Ag

Inventors

• Gutmann Alois
• Hampp Roland
• Jansen Scott

Classifications

• H10D62/80

  characterised by the materials · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title