Semiconductor devices with field plates

Patent metadata

Field	Value
Publication number	US-9373699-B2
Application number	US-201514660080-A
Country	US
Kind code	B2
Filing date	Mar 17, 2015
Priority date	Aug 28, 2009
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

First claim

What is claimed is:

1. A method of forming a III-N device, comprising:
a providing a III-N material layer;
forming an insulator layer on a surface of the III-N material layer;
forming an electrode defining layer on an opposite side of the insulator layer from the III-N material layer, wherein a recess having a first sidewall and a second sidewall is formed in the electrode defining layer, the first sidewall being on an opposite side of the recess from the second sidewall, the first and second sidewalls each extending from a first surface of the electrode defining layer to a second surface of the electrode defining layer, the first surface being adjacent to the insulator layer and the second surface being opposite the first surface;
forming a gate electrode in the recess and over the first and second sidewalls;
forming a source; and
forming a drain on an opposite side of the recess from the source, the source being proximal to the first sidewall and the drain being proximal to the second sidewall; wherein
a first angle is formed between a surface of the insulator layer and a portion of the first sidewall, the portion of the first sidewall being adjacent to the surface of the insulator layer;
a second angle is formed between the surface of the insulator layer and a portion of the second sidewall, the portion of the second sidewall being adjacent to the surface of the insulator layer; and
the first angle is greater than the second angle.

2. The method of claim 1 , further comprising forming an etch stop layer between the insulator layer and the electrode defining layer.

3. The method of claim 1 , the first angle being substantially greater than the second angle, wherein a gate-source capacitance of the device is reduced as compared to a similar device in which the first angle is about the same as the second angle.

4. The method of claim 1 , wherein the recess formed in the electrode defining layer is also formed in a portion of the insulator layer.

5. A device, comprising:
a III-N material layer;
an insulator layer on a surface of the III-N material layer;
an electrode defining layer on an opposite side of the insulator layer from the material layer, wherein a recess having a first sidewall and a second sidewall is formed in the electrode defining layer, the first sidewall being on an opposite side of the recess from the second sidewall, the first and second sidewalls each extending from a first surface of the electrode defining layer to a second surface of the electrode defining layer, the first surface being adjacent to the insulator layer and the second surface being opposite the first surface;
a gate electrode in the recess and over the first and second sidewalls;
a source; and
a drain on an opposite side of the recess from the source, the source being proximal to the first sidewall and the drain being proximal to the second sidewall; wherein
a first angle is formed between a surface of the insulator layer and a portion of the first sidewall, the portion of the first sidewall being adjacent to the surface of the insulator layer;
a second angle is formed between the surface of the insulator layer and a portion of the second sidewall, the portion of the second sidewall being adjacent to the surface of the insulator layer; and
the first angle is greater than the second angle.

6. The device of claim 5 , further comprising an etch stop layer between the insulator layer and the electrode defining layer.

7. The device of claim 5 , the first angle being substantially greater than the second angle, wherein a gate-source capacitance of the device is reduced as compared to a similar device in which the first angle is about the same as the second angle.

8. The device of claim 5 , wherein the second angle is between 30 and 45 degrees.

9. The device of claim 5 , wherein the first angle is between 45 and 90 degrees.

10. The device of claim 5 , wherein the recess formed in the electrode defining layer is also formed in a portion of the insulator layer.

11. A III-N device, comprising:
a III-N material layer;
an insulator layer on a surface of the III-N material layer;
a first electrode defining layer on an opposite side of the insulator layer from the III-N material layer;
a stack on an opposite side of the first electrode defining layer from the insulator layer, wherein the stack comprises an etch stop layer and a second electrode defining layer, and a recess is formed in the stack and in the first electrode defining layer; and
an electrode formed in the recess; wherein
the electrode covers a portion of a top surface of the stack.

12. The device of claim 11 , wherein the electrode includes a field plate.

13. The device of claim 12 , wherein the field plate is a slant field plate.

14. The device of claim 13 , wherein a portion of the recess in the first electrode defining layer has angled walls with at least a portion that is at a non-perpendicular angle to a main surface of the first etch stop layer, the angled walls defining the slant field plate.

15. The device of claim 14 , wherein the device is a FET which further comprises a drain.

16. The device of claim 11 , wherein the insulator layer is formed of an oxide or nitride.

17. The device of claim 11 , wherein the first electrode defining layer is formed of an oxide or nitride.

18. The device of claim 11 , wherein the first electrode defining layer is at least 100 nanometers thick.

19. The device of claim 11 , wherein the first electrode defining layer and the insulator layer are formed of different materials.

20. The device of claim 11 , wherein the recess is also formed in the insulator layer.

21. The device of claim 20 , wherein a first portion of the III-N material layer has a first composition and a second portion of the III-N material layer has a second composition, wherein a difference between the first composition and the second composition forms a 2DEG channel in the III-N material layer.

22. The device of claim 21 , further comprising a cathode, wherein a portion of the electrode is an anode, the anode forms a substantially Schottky contact to the III-N material layer, and the cathode is in electrical contact with the 2DEG channel.

23. The device of claim 22 , wherein the recess extends into the III-N material layer and the electrode is in a portion of the recess in the III-N material layer.

24. The device of claim 23 , wherein the recess extends through the 2DEG channel.

25. The device of claim 11 , wherein a first portion of the III-N material layer has a first composition and a second portion of the III-N material layer has a second composition, wherein a difference between the first composition and the second composition forms a 2DEG channel in the III-N material layer.

26. The device of claim 11 , wherein the electrode comprises a gate, and the device further comprises a source and a drain.

27. A III-N device, comprising:
a III-N material layer;
an insulator layer on a surface of the III-N material layer;
a first electrode defining layer on an opposite side of the insulator layer from the III-N material layer;
a first electrode, wherein a first recess is formed in the first electrode defining layer and the first electrode is formed in the first recess; and
a stack on an opposite side of the first electrode defining layer from the insulator layer, wherein the stack comprises an etch stop laye

Assignees

• Transphorm Inc

Inventors

• Chu Rongming
• Coffie Robert

Classifications

• H10P50/646

  of Group III-V materials · CPC title

• H10P50/282

  of inorganic materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title