Semiconductor device and method for manufacturing the same

US9373676B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9373676-B2
Application numberUS-201313734279-A
CountryUS
Kind codeB2
Filing dateJan 4, 2013
Priority dateSep 11, 2006
Publication dateJun 21, 2016
Grant dateJun 21, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug 46 buried in the insulation layer, a capacitor formed above the insulation layer and the conductor plug and including a lower electrode formed of the first conduction film and the second conduction film formed over the first conduction film and formed of Pt, Pt alloy, Pd or Pd alloy, a capacitor dielectric film formed of a ferroelectric or a high dielectric formed over the lower electrode and an upper electrode formed over the capacitor dielectric film, the capacitor dielectric film contains a first element of Pb or Bi, and the concentration peak of the first element diffused in the lower electrode from the capacitor dielectric film positioning in the interface between the first conduction film and the second conduction film.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for manufacturing a semiconductor device comprising a capacitor including a lower electrode, a capacitor dielectric film of a ferroelectric or a high dielectric formed over the lower electrode and an upper electrode formed over the capacitor dielectric film, comprising: forming a transistor over a semiconductor substrate; forming an insulation layer over the semiconductor substrate and over the transistor; burying a conductor plug in the insulation layer so that the conductor plug is electrically coupled to the transistor; forming over the insulation layer and the conductor plug, the lower electrode including a first conduction film and a second conduction film formed over the first conduction film; forming the capacitor dielectric film over the lower electrode, the capacitor dielectric film containing a first element of Pb or Bi, and forming the upper electrode over the capacitor dielectric film wherein the lower electrode prevents the diffusion of the first element at an interface between the first conduction film and the second conduction film, the method further comprising, after the burying the conductor plug and before forming the first conduction film, forming a conducting oxygen barrier film for preventing oxidation of the conduction plug, wherein a concentration profile of the first element across the lower electrode along a direction perpendicular to the interface has a concentration peak in the interface between the first conduction film and the second conduction film. 2. The method for manufacturing a semiconductor device according to claim 1 , wherein the first conduction film is formed of a platinum oxide or a palladium oxide; and the second conduction film is Pt, a Pt alloy, Pd or a Pd alloy. 3. The method for manufacturing a semiconductor device according to claim 1 , wherein the lower electrode further comprises: forming a third conduction film of Pt, a Pt alloy, Pd or a Pd alloy formed over the second conduction film. 4. The method for manufacturing a semiconductor device according to claim 1 , further comprising, after forming the lower electrode and before forming the capacitor dielectric film: performing thermal processing in an atmosphere of an inert gas to partially reduce the lower electrode. 5. The method for manufacturing a semiconductor device according to claim 1 , wherein forming the capacitor dielectric film includes forming a first dielectric film over the lower electrode by sputtering or a sol-gel process and forming a second dielectric film over the first dielectric film by metal organic chemical vapor deposition. 6. The method for manufacturing a semiconductor device according to claim 1 , wherein the oxygen barrier film is formed of TiAIN, TiAION, TaAIN or TaAION. 7. The method for manufacturing a semiconductor device according to claim 6 , further comprising, after burying the conductor plug and before forming the oxygen barrier film: forming a conducting adhesion layer for improving crystallinity of the oxygen barrier film and for improving adhesion between the oxygen barrier film and the insulation layer. 8. The method for manufacturing a semiconductor device according to claim 7 , further comprising, after burying the conductor plug and before forming the adhesion layer: exposing a surface of the insulation layer and a surface of the conduction plug to a plasma containing nitrogen. 9. The method for manufacturing a semiconductor device according to claim 8 , wherein the plasma containing nitrogen is NH 3 plasma or N 2 plasma. 10. The method for manufacturing a semiconductor device according to claim 6 , further comprising, after burying the conductor plug and before forming the oxygen barrier film: forming a base layer; and polishing a surface of the base layer to planarize the surface of the base layer. 11. The method for manufacturing a semiconductor device according to claim 6 , further comprising, after burying the conductor plug and before forming the oxygen barrier film: burying a base layer in a cavity formed in a part of the conductor plug where the conductor plug has been buried.

Assignees

Inventors

Classifications

  • H10D1/682Primary

    having dielectrics comprising perovskite structures · CPC title

  • H10D1/68Primary

    Capacitors having no potential barriers · CPC title

  • Electricity · mapped topic

  • H01L28/40Primary

    Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9373676B2 cover?
The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug 46 buried in the insulation layer, a capacitor formed above the insulation layer and the conductor plug and including a lower electrode formed of the first conduction film and the second conduction film formed over the first conduction film and formed of Pt, Pt alloy, Pd or Pd alloy, a cap…
Who is the assignee on this patent?
Fujitsu Ltd Fujitsu Semiconductor Ltd, Fujitsu Semiconductor Ltd
What technology area does this patent fall under?
Primary CPC classification H10D1/682. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 21 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).