Semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9373628-B2
Application number	US-201414171056-A
Country	US
Kind code	B2
Filing date	Feb 3, 2014
Priority date	Feb 4, 2013
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

First claim

What is claimed is:

1. A method of fabricating a semiconductor memory device, comprising:
forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate;
forming a channel hole to penetrate the electrode structure;
forming a data storage layer on a sidewall of the channel hole; and
forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate,
forming a trench penetrating the electrode structure;
partially removing the electrode layers exposed by the trench to form first recess regions;
forming conductive patterns in the first recess regions to be in contact with the electrode layers; and
sequentially forming an insulating spacer and a through electrode in the trench,
wherein the electrode layers are metal-silicide layers, and the insulating layers and the electrode layers are formed in an in-situ manner using the same deposition system.

2. The method of claim 1 , wherein the deposition system comprises a first chamber, in which the electrode layers are formed, and a second chamber, in which the insulating layers are formed.

3. The method of claim 2 , wherein the first chamber is a PVD chamber and the second chamber is a CVD chamber.

4. The method of claim 3 , wherein the electrode layers are formed using a metal-silicide target.

5. The method of claim 3 , wherein the electrode layers are formed using a metal target and a silicon target.

6. The method of claim 1 , further comprising forming a metal-silicide layer between the through electrode and the substrate.

7. The method of claim 1 , wherein the conductive patterns comprises a conductive metal nitride.

8. The method of claim 1 , further comprising:
selectively removing the insulating layers exposed by the trench to form second recess regions; and
forming an additional insulating layer defining air gaps in the second recess regions.

9. The method of claim 8 , wherein the forming of the insulating spacer comprises anisotropically etching the additional insulating layer.

10. A method of fabricating a semiconductor memory device, comprising:
forming, in an in-situ manner using a same deposition system, an electrode structure comprising insulating layers and electrode layers alternatingly stacked on a substrate;
forming a channel hole to penetrate the electrode structure;
for a data storage layer on a sidewall of the channel hole, wherein the electrode layers comprise metal-silicide layers; and
forming a metal nitride layer between the electrode layers and the data storage layer,
wherein forming the electrode layers comprises a sputtering process using a metal-silicide and/or silicon target.

11. The method of claim 10 , wherein the deposition system comprises a first chamber, in which the electrode layers are formed, and a second chamber, in which the insulating layers are formed.

12. The method of claim 11 , wherein the first chamber and the second chamber are part of a same vacuum system, and wherein forming an electrode structure comprises:
transferring the substrate between the first chamber and the second chamber without substantial breakage of a vacuum level.

13. The method of claim 11 , wherein the first chamber and the second chamber have different vacuum levels.

14. The method of claim 11 , further comprising:
performing a first deposition process in the first chamber to form each electrode layer; and
performing a second deposition process in the second chamber to form each insulating layer, wherein the first and second deposition processes are different.

15. The method of claim 10 , further comprising:
forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate;
forming a trench penetrating the electrode structure;
sequentially forming an insulating spacer and a through electrode in the trench; and
forming a metal-silicide layer between the through electrode and the substrate.

16. A method of fabricating a semiconductor memory device, comprising:
forming, in an in-situ manner using a same deposition system, an electrode structure comprising first insulating layers and metal-silicide electrode layers alternatingly stacked on a substrate, wherein the insulating layers are formed in a first chamber of the same deposition system and the metal-silicide electrode layers are formed in a second chamber of the same deposition system;
forming a channel hole to penetrate the electrode structure through to the substrate;
forming a trench to penetrate the electrode structure through to the substrate;
removing the first insulating layers exposed by the channel hole and the trench to form first recess regions;
forming second insulating layers in the first recess regions using a deposition technique providing a step coverage property such that the second insulating layers in the first recess regions have air gaps;
partially removing the electrode layers exposed by the channel hole to form second recess regions;
forming a metal-nitride conductive layer in the channel hole;
partially removing the metal-nitride conductive layer to form metal-nitride conductive patterns in the second recess regions, the metal-nitride conductive patterns contacting the electrode layers;
forming a data storage layer on a sidewall of the channel hole to be in contact with the metal-nitride conductive patterns;
forming a first semiconductor pattern on a sidewall of the data storage layer;
forming a second semiconductor pattern on a sidewall of the first semiconductor pattern to be electrically connected to the substrate;
sequentially forming an insulating spacer and a through electrode in the trench; and
forming a metal-silicide layer between the through electrode and the substrate.

Assignees

• Sohn Woonghee
• Yun Kihyun
• Lee Myoungbum
• Lee Jeonggil
• Lim Tai-Soo
• Jung Yong Chae
• Samsung Electronics Co Ltd

Inventors

• Sohn Woonghee
• Yun Kihyun
• Lee Myoungbum
• Lee Jeonggil
• Lim Tai-Soo
• Jung Yong Chae

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0411 Primary

  of FETs having floating gates · CPC title