Methods and apparatuses to form self-aligned caps

Patent metadata

Field	Value
Publication number	US-9373584-B2
Application number	US-201113991899-A
Country	US
Kind code	B2
Filing date	Nov 4, 2011
Priority date	Nov 4, 2011
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

First claim

What is claimed is:

1. A method to manufacture an electronic device, comprising:
recessing at least one conductive line in a dielectric layer over a substrate to form a channel comprising a dielectric sidewall using a first chemistry comprising between about 0.1% to about 70% by mass of an etchant, between about 0.1% to about 10% by mass of an oxidizer, between about 50 ppm to about 1% by mass of an inhibitor and between about 1% to about 60% by mass of a solvent to provide an etching uniformity independent of a crystallographic orientation; and
depositing a capping layer on the recessed conductive line and on the dielectric sidewall of the channel to prevent electromigration.

2. The method of claim 1 , wherein the recessing includes forming a passivation layer on the at least one conductive line during etching using the inhibitor and the solvent, wherein the passivation layer is to ensure that the at least one conductive line is etched uniformly independent of a crystallographic orientation.

3. The method of claim 1 , wherein the channel is self-aligned to the conductive line.

4. The method of claim 1 , wherein the at least one conductive line is recessed to a depth determined based on a thickness of the capping layer.

5. The method of claim 1 , wherein the capping layer is deposited on the recessed conductive line by an electroless plating, a chemical vapor deposition, or a physical vapor deposition.

6. The method of claim 1 , further comprising
forming a dielectric layer over the substrate;
forming at least one opening in the dielectric layer; and
filling the at least one opening with a conductive material to form the at least one conductive line.

7. The method of claim 1 , wherein the at least one conductive line comprises a first metal, and the capping layer comprises a second metal other than the first metal.

8. A method to control line edge roughness, comprising:
etching at least one conductive line in a dielectric layer over a substrate with a first chemistry to a predetermined depth to form a channel comprising a dielectric sidewall self-aligned to the at least one conductive line, wherein the first chemistry comprises between about 0.1% to about 70% by mass of an etchant, between about 0.1% to about 10% by mass of an oxidizer, between about 50 ppm to about 1% by mass of an inhibitor and between about 1% to about 60% by mass of a solvent to provide uniformity of etching independent of a crystallographic orientation; and
depositing a capping layer on the at least one conductive line and on the dielectric sidewall of the channel.

9. The method of claim 8 , wherein the etchant includes a glycine, an ethylenediaminetetraacetic acid, an alpha-amino acid, a polycarboxylic acid, or a combination thereof; the oxidizer includes a peroxide, an ozone, a permanganate, a chromate, a perborate, a hypohalite, or a combination thereof, the inhibitor includes an azole, an amine, an amino acid, a phosphate, a phosphonate, or a combination thereof, and the solvent includes water, propylene carbonate, sulfolane, glycol ethers, methylene chloride, or any combination thereof.

10. The method of claim 8 , further comprising
depositing the capping layer onto the etched conductive line in the channel.

11. The method of claim 8 , wherein the depth is determined based on a thickness of the capping layer.

Assignees

• Boyanov Boyan
• Singh Kanwal Jit
• Intel Corp

Inventors

• Boyanov Boyan
• Singh Kanwal Jit

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title