Lead frame, manufacture method and package structure thereof

Patent metadata

Field	Value
Publication number	US-9373567-B2
Application number	US-201414459515-A
Country	US
Kind code	B2
Filing date	Aug 14, 2014
Priority date	Aug 14, 2013
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

Disclosed herein are various chip lead frame and packaging structures, and methods of fabrication. In one embodiment, a lead frame can include: (i) a horizontal plate arranged at a bottom of the lead frame, where the horizontal plate is conductive; and (ii) a plurality of conductive bumps arranged on a surface of the horizontal plate, where the plurality of conductive bumps are configured to support and electrically connect to at least one chip. In one embodiment, a method of making the lead frame can include: (i) forming the horizontal plate by a mold; (ii) arranging a mask with a through-hole on the surface of the horizontal plate; (iii) electroplating conducting material on a portion of the horizontal plate that is exposed by the through-hole; and (iv) removing the mask after formation of the plurality of conductive bumps. Also, a package structure can be formed using the lead frame.

First claim

What is claimed is:

1. A method of making a package structure, the method comprising:
a) forming a horizontal plate and a plurality of first conductive bumps by two separate molds, wherein said horizontal plate is conductive and arranged at a bottom of a lead frame;
b) stamping said plurality of first conductive bumps on corresponding locations of said horizontal plate;
c) arranging a first component above and electrically connected to said horizontal plate of said lead frame by said plurality of first conductive bumps;
d) forming a plurality of second conductive bumps on said horizontal plate outside of a region covered by said first component, wherein each of said plurality of second bumps extends to a height greater than said first component;
e) forming a plurality of third conductive bumps on said plurality of second conductive bumps; and
f) arranging a second component above said first component and electrically connecting said second component to said plurality of third conductive bumps.

2. The method of claim 1 , wherein said first component comprises a chip.

3. The method of claim 1 , wherein said second component comprises a magnetic component.

4. The method of claim 1 , further comprising an adhesive layer arranged between said first and second components.

5. The method of claim 1 , wherein each of said plurality of first, second, and third conductive bumps comprises a spherical shape.

6. The method of claim 1 , wherein each of said plurality of first, second, and third conductive bumps comprises copper material.

7. The method of claim 1 , wherein each of said plurality of first, second, and third conductive bumps comprises a rectangular shape.

8. The method of claim 1 , wherein each of said plurality of first, second, and third conductive bumps comprises a cylindrical shape.

9. The method of claim 1 , wherein each of said plurality of first, second, and third conductive bumps comprises tin material.

10. The method of claim 1 , wherein each of said plurality of first, second, and third conductive bumps comprises nickel material.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Tan Xiaochun

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title