Vertical structure semiconductor memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9373400-B2
Application number	US-201514960839-A
Country	US
Kind code	B2
Filing date	Dec 7, 2015
Priority date	Jun 7, 2010
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor region extending vertically from a first region of a substrate;
a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, the plurality of gate electrodes being separated from one another and being disposed along a sidewall of the semiconductor region;
a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes;
a substrate contact electrode extending vertically from an impurity-doped second region of the substrate,
the substrate contact electrode extending from the substrate to a height greater than that of an uppermost gate electrode from among the plurality of gate electrodes; and

an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes, wherein
the semiconductor region, plurality of gate electrode, and gate dielectric layer define a memory cell string extending vertically from the first region of the substrate; and
the insulating region is between the memory cell string and the substrate contact electrode.

2. A semiconductor memory device comprising:
a semiconductor region extending vertically from a first region of a substrate;
a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, the plurality of gate electrodes being separated from one another and being disposed along a sidewall of the semiconductor region;
a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes;
a substrate contact electrode extending vertically from an impurity-doped second region of the substrate,
the substrate contact electrode extending from the substrate to a height greater than that of an uppermost gate electrode from among the plurality of gate electrodes;

an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes;
at least one memory cell string on the first region of the substrate and extending in a first direction, the first direction being substantially perpendicular to a surface of the substrate, the memory cell string including the semiconductor region, the plurality of gate electrodes, and the gate dielectric layer;
a substrate contact electrode disposed on the impurity-doped second region of the substrate and extending in the first direction,
the substrate contact electrode being insulated from the at least one memory cell string by the air gap; and
one of a core circuit unit, a controller, and a processor connected to the semiconductor memory device.

3. A memory device comprising:
a NAND cell array including at least one semiconductor memory device of claim 2 ; wherein
the core circuit unit is connected to the at least one semiconductor memory device,
the core circuit unit is configured to communicate with the NAND cell array, and
the core circuit includes,
a row decoder configured to communicate with the NAND cell array via a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines,

a column decoder configured to communicate with the NAND cell array via a plurality of bit lines,
a sense amplifier configured to communicate with the column decoder, and
a control logic unit configured to communicate with the row decoder and the column decoder.

4. A memory card comprising:
a memory unit including at least one semiconductor memory device of claim 2 , wherein the controller is connected to the at least one semiconductor memory device and
the controller is configured to exchange electrical signals with the memory unit.

5. An electronic system comprising:
an input/output unit configured to input data to or output data from the electronic system; and
a memory unit including at least one semiconductor memory device of claim 2 , wherein
the processor is connected to the at least one semiconductor memory device,
the memory unit is configured to store at least one of code and data for operating the processor, and
the processor, the input/output unit and the memory unit are coupled to one another via a bus.

Assignees

• Hwang Sung-Min
• Kim Han-Soo
• Shim Sun-Il
• Samsung Electronics Co Ltd

Inventors

• Hwang Sung-Min
• Kim Han-Soo
• Shim Sun-Il

Classifications

• H10D84/837

  comprising vertical IGFETs · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title