Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9373389-B2
Application number	US-201614989753-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Jul 2, 2013
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern includes read word lines, read bit lines, and read source lines. Each of the plurality of memory cells includes: first and second inverters which are cross-coupled to each other; a first transistor which is connected between a read bit line and a read source line and of which the gate is connected to the output terminal of the first inverter; and a second transistor which is connected in series to the first transistor and of which the gate is connected to a read word line.

First claim

What is claimed is:

1. A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern, the device comprising:
a plurality of read word lines, each of which is provided for an associated one of the rows of the memory cell array and connected in common to a plurality of memory cells that form the associated row;
a plurality of read bit lines, each of which is provided for an associated one of the columns of the memory cell array and connected in common to a plurality of memory cells that form the associated column; and
a plurality of read source lines, each of which is provided for an associated one of the columns of the memory cell array and connected in common to a plurality of memory cells that form the associated column, wherein
each of the plurality of memory cells includes:
first and second inverters which are cross-coupled to each other;
a first transistor which is connected between a read bit line and a read source line that are associated with the memory cell and of which the gate is connected to the output terminal of the first inverter; and
a second transistor which is connected in series to the first transistor and of which the gate is connected to a read word line that is associated with the memory cell.

2. The semiconductor memory device of claim 1 , wherein
in each of the plurality of memory cells,
the first transistor has its drain connected to a read bit line associated with the memory cell and has its source connected to the drain of the second transistor, and
the second transistor has its source connected to a read source line associated with the memory cell.

3. The semiconductor memory device of claim 1 , wherein
in each of the plurality of memory cells,
the first transistor has its source connected to a read source line associated with the memory cell and has its drain connected to the source of the second transistor, and
the second transistor has its drain connected to a read bit line associated with the memory cell.

4. The semiconductor memory device of claim 1 , further comprising:
a plurality of write bit lines, each of which is provided for an associated one of the columns of the memory cell array and connected in common to a plurality of memory cells that form the associated column; and
a plurality of inverted write bit lines, each of which is provided for an associated one of the columns of the memory cell array and connected in common to a plurality of memory cells that form the associated column, wherein
each of the plurality of memory cells includes:
a third transistor connected between a write bit line associated with the memory cell and the input terminal of the first inverter; and
a fourth transistor connected between an inverted write bit line associated with the memory cell and the input terminal of the second inverter.

5. The semiconductor memory device of claim 1 , wherein
one of the plurality of read source lines which is associated with a selected one of the columns of the memory cell array is controlled to be active.

6. The semiconductor memory device of claim 5 , wherein
while data is being read from a selected one of the plurality of memory cells, a read source line associated with the selected column including the selected memory cell is connected to a ground potential, and the other read source lines are connected to the same potential as read bit lines associated with the non-selected columns other than the selected column.

7. The semiconductor memory device of claim 1 , further comprising
a plurality of keeper circuits, each of which is provided for an associated one of the plurality of read bit lines and which is configured to keep a potential on the associated read bit line a predetermined potential.

8. The semiconductor memory device of claim 7 , wherein
each of the plurality of keeper circuits includes:
a third inverter, of which the input terminal is connected to a read bit line associated with the keeper circuit; and
a fifth transistor, of which the gate is connected to the output terminal of the third inverter, the source is connected to the predetermined potential, and the drain is connected to the read bit line associated with the keeper circuit.

9. The semiconductor memory device of claim 1 , further comprising
a plurality of driver circuits, each of which is provided for an associated one of the plurality of read source lines, wherein
while data is being read from a selected one of the plurality of memory cells, a potential applied to a driver circuit which activates a read source line associated with a selected one of the columns of the memory cell array, including the selected memory cell, is controlled to be a predetermined potential which is higher than a potential applied to the other driver circuits.

10. The semiconductor memory device of claim 9 , further comprising
a plurality of booster circuits, each of which is provided for an associated one of the plurality of driver circuits and which has the ability to generate the predetermined potential, wherein
each of the plurality of driver circuits includes:
a fourth inverter which operates using, as its power supply, output of one of the booster circuits that is associated with the driver circuit; and
a fifth inverter, of which the input terminal is connected to the output terminal of the fourth inverter and the output terminal is connected to a read source line associated with the driver circuit.

11. The semiconductor memory device of claim 1 , further comprising
a plurality of precharge circuits, each of which is provided for an associated one of the plurality of read bit lines and which precharges the associated read bit line to a predetermined potential, wherein
a timing for the plurality of precharge circuits to stop precharging is later than a timing when one of the plurality of read source lines that is associated with a selected column of the memory cell array is discharged.

Assignees

• Socionext Inc

Inventors

• Yamamoto Yasue

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G11C11/412

  using field-effect transistors only · CPC title