Method and device for managing a key matrix, corresponding computer program product and storage device

US9372547B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9372547-B2
Application numberUS-201214354844-A
CountryUS
Kind codeB2
Filing dateOct 25, 2012
Priority dateOct 28, 2011
Publication dateJun 21, 2016
Grant dateJun 21, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for managing, by device, a matrix of keys, including at least one line and at least two columns, each key making short circuiting a line and a column when pressed. The method includes a sweeping phase, including, for each line: writing a predetermined logic value in the line; and for each column, reading a logic value in the column and comparing the read logic value and the predetermined logic value. For each line processed: the writing step is carried out during a predetermined time interval. For each column, the reading step is carried out during a first portion of the time interval. The sweeping phase further includes, for each column, writing the predetermined logic value in the column during a second portion of the predetermined time interval. The predetermined time interval is equal to the sum of the durations of the first and second portions.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for management, by a device, of a matrix of keys comprising at least one row and at least two columns, each key making it possible, when it is pressed, to short-circuit a row and a column of said matrix, the method comprising at least one iteration of a scan phase comprising the following steps performed by the device for each of the rows processed successively: writing a predetermined logic value to the row; and for each column, reading a logic value on the column and determining whether the column is short-circuited with the row, by comparison between the logic value read and the predetermined logic value, wherein, for each of the rows processed successively: the step of writing the predetermined logic value to the row is performed during a predetermined time slot; during said predetermined time slot, for each of said columns: the step of reading a logic value on the column is performed during a first part of said predetermined time slot; and the scan phase comprises an additional step of writing the predetermined logic value to the column during a second part of said predetermined time slot, the duration of said predetermined time slot being equal to the sum of the durations of the first and second parts. 2. The method according to claim 1 , wherein, for each column, the order of steps of reading and writing during the predetermined time slot is selected randomly. 3. The method according to claim 2 , wherein, in each predetermined time slot, the duration of the second part of the predetermined time slot is identical for all the columns. 4. The method according to claim 1 , wherein the matrix of keys comprises a plurality of rows and, at each iteration of the scan phase, the order of successive processing of the rows is random. 5. The method according to claim 1 , wherein the matrix of keys comprises a plurality of rows and, wherein, during a given iteration of the scan phase, at least one parameter varies randomly from one row to the other, said at least one parameter belonging to the group consisting of: the duration of the predetermined time slot; the duration of the first part of the predetermined time slot; and the duration of the second part of the predetermined time slot. 6. The method according to claim 1 , wherein, at least one iteration of the scan phase, which follows an iteration during which at least one short-circuit has been determined between a given column and a given row, comprises the following steps: for each of the successively processed rows, other than a given row that is short-circuited with a given column: for each column, writing the predetermined logic value to the column throughout the duration of the time slot; for each given row short-circuited with a given column: for each column other than the given column, writing the predetermined logic value to the column throughout the duration of the time slot; and for the given column, reading a logic value during the first part of the time slot in order to detect a continuing or a stopping of said short-circuit between the given column and the given row, and writing the predetermined logic value during the second part of the time slot. 7. A computer readable and non-transient storage medium storing a computer program comprising a set of instructions executable by a computer or a processor to implement a method for managing, by a device, a matrix of keys comprising at least one row and at least two columns, each key making it possible, when it is pressed, to short-circuit a row and a column of said matrix, the method comprising at least one iteration of a scan phase comprising the following steps performed by the device for each of the rows processed successively: writing a predetermined logic value to the row; and for each column, reading a logic value on the column and determining whether the column is short-circuited with the row, by comparison between the logic value read and the predetermined logic value, wherein, for each of the rows processed successively: the step of writing the predetermined logic value to the row is performed during a predetermined time slot; during said predetermined time slot, for each of said columns: the step of reading a logic value on the column is performed during a first part of said predetermined time slot; and the scan phase comprises an additional step of writing the predetermined logic value to the column during a second part of said predetermined time slot, the duration of said predetermined time slot being equal to the sum of the durations of the first and second parts. 8. A device for managing a matrix of keys comprising at least one row and at least two columns, each key making it possible, when it is pressed, to short-circuit a row and a column of said matrix, the device comprising: means for scanning, which carries out at least one iteration of a scan phase, the means for scanning comprising the following means, activated for each of the rows processed successively: means for writing a predetermined logic value to the row; and means for reading a logic value on each column to determine whether the column is shorted-circuited with the row, by comparison between the logic value read and the predetermined logic value, wherein the means for scanning comprise additional means for writing, and wherein, for each of the rows processed successively: the means for writing the predetermined logic value to the row are activated during a predetermined time slot; during said predetermined time slot, for each of said columns: the means for reading the logic value on the column are activated during a first part of said predetermined time slot; the additional means for writing are activated during a second part of said predetermined time slot to write the predetermined logic value to the column, the duration of the predetermined time slot being equal to the sum of durations of the first and second parts.

Assignees

Inventors

Classifications

  • Measures for preventing unauthorised decoding of keyboards · CPC title

  • Programmable keyboards (key guide holders G06F3/0224) · CPC title

  • G06F21/83Primary

    input devices, e.g. keyboards, mice or controllers thereof · CPC title

  • Coding of multifunction keys · CPC title

  • G06F3/02Primary

    Input arrangements using manually operated switches, e.g. using keyboards or dials · CPC title

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Frequently asked questions

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What does patent US9372547B2 cover?
A method for managing, by device, a matrix of keys, including at least one line and at least two columns, each key making short circuiting a line and a column when pressed. The method includes a sweeping phase, including, for each line: writing a predetermined logic value in the line; and for each column, reading a logic value in the column and comparing the read logic value and the predetermin…
Who is the assignee on this patent?
Ingenico Sa, Ingenico Group
What technology area does this patent fall under?
Primary CPC classification G06F21/83. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 21 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).