Alignment of single-mode polymer waveguide (PWG) array and silicon waveguide (SIWG) array of providing adiabatic coupling

Patent metadata

Field	Value
Publication number	US-9372305-B2
Application number	US-201314050450-A
Country	US
Kind code	B2
Filing date	Oct 10, 2013
Priority date	Oct 18, 2012
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A method for fabricating, and a structure embodying, a single-mode polymer wave guide array aligned with a polymer waveguide array through adiabatic coupling. The present invention provides a structure having a combination of (i) a stub fabricated on a polymer and (ii) a groove fabricated on a silicon (Si) chip, with which an adiabatic coupling can be realized by aligning (a) a (single-mode) polymer waveguide (PWG) array fabricated on the polymer with (b) a silicon waveguide (SiWG) array fabricated on the silicon chip; wherein, the stub fabricated on the polymer is patterned according to a nano-imprint process, along with the PWG array, in a direction in which the PWG array is fabricated, and the groove fabricated on the silicon chip is fabricated along a direction in which the SiWG array is fabricated.

First claim

What is claimed is:

1. A method of fabricating on a polymer a (single-mode) polymer waveguide (PWG) array and a stub so that the (single-mode) polymer waveguide (PWG) array and the stub are aligned with a silicon waveguide (SiWG) array fabricated on a silicon (Si) chip and a groove fabricated along a direction in which the SiWG is fabricated, whereby an adiabatic coupling is realized, the method comprising the steps of:
preparing a polymer base layer;
placing on the polymer base layer a cast having a groove corresponding to a core of the (single-mode) polymer waveguide (PWG) array and a groove corresponding to the stub;
hardening the polymer base layer; and
removing the cast from the hardened polymer base layer.

2. The method according to claim 1 , further comprising the steps of:
preparing the silicon (Si) chip having the silicon waveguide (SiWG) array and the groove fabricated thereon;
preparing the polymer having the (single-mode) polymer waveguide (PWG) array and the stub fabricated thereon;
aligning the silicon chip with the polymer so that a spatial relationship is provided to realize the adiabatic coupling; and
securing the silicon chip and the polymer by use of an optical epoxy or a UV adhesive.

3. The method according to claim 2 , further comprising the steps of:
preparing an MTP connector secured to the polymer;
preparing an interposer secured to the silicon chip; and
encapsulating these.

4. The method according to claim 3 , further comprising the steps of:
preparing a heat sink secured to the silicon chip;
preparing a cover plate (the outer shell of a package); and
covering the whole body by the cover plate.

5. The method according to claim 1 ,
wherein the width of core of the (single-mode) polymer waveguide (PWG) array fabricated on the polymer is approximately 5 μm, and the width of core of the silicon waveguide (SiWG) array fabricated on the silicon (Si) chip is approximately several hundred nm to 1 μm.

6. The method according to claim 1 ,
wherein both the material of the core used to fabricate the core array by the photolithography process with the first mask and the material of the base layer used to fabricate the stub by the photolithography process with the second mask are selected from the same type polymer materials, such as acrylic, epoxy or polyimide, and
wherein a developer and a rinse liquid used in the photolithography process with the first mask can be used again as it is as a developer and a rinse liquid used in the photolithography process with the second mask.

7. A combination of a stub fabricated on a polymer and a groove fabricated on a silicon (Si) chip, prepared by a method of fabricating on a polymer a (single-mode) polymer waveguide (PWG) array and a stub so that the (single-mode) polymer waveguide (PWG) array and the stub are aligned with a silicon waveguide (SiWG) array fabricated on a silicon (Si) chip and a groove fabricated along a direction in which the SiWG is fabricated, whereby an adiabatic coupling is realized, the method comprising the steps of:
preparing a polymer base layer;
placing on the polymer base layer a cast having a groove corresponding to a core of the (single-mode) polymer waveguide (PWG) array and a groove corresponding to the stub;
hardening the polymer base layer; and
removing the cast from the hardened polymer base layer.

8. The method according to claim 7 , further comprising the steps of:
preparing the silicon (Si) chip having the silicon waveguide (SiWG) array and the groove fabricated thereon;
preparing the polymer having the (single-mode) polymer waveguide (PWG) array and the stub fabricated thereon;
aligning the silicon chip with the polymer so that a spatial relationship is provided to realize the adiabatic coupling; and
securing the silicon chip and the polymer by use of an optical epoxy or a UV adhesive.

9. The method according to claim 7 , further comprising the steps of:
preparing an MTP connector secured to the polymer;
preparing an interposer secured to the silicon chip; and
encapsulating these.

10. The method according to claim 7 , further comprising the steps of:
preparing a heat sink secured to the silicon chip;
preparing a cover plate (the outer shell of a package); and
covering the whole body by the cover plate.

11. The method according to claim 7 ,
wherein the width of core of the (single-mode) polymer waveguide (PWG) array fabricated on the polymer is approximately 5 μm, and the width of core of the silicon waveguide (SiWG) array fabricated on the silicon (Si) chip is approximately several hundred nm to 1 μm.

12. The method according to claim 7 ,
wherein both the material of the core used to fabricate the core array by the photolithography process with the first mask and the material of the base layer used to fabricate the stub by the photolithography process with the second mask are selected from the same type polymer materials, such as acrylic, epoxy or polyimide, and
wherein a developer and a rinse liquid used in the photolithography process with the first mask can be used again as it is as a developer and a rinse liquid used in the photolithography process with the second mask.

Assignees

• IBM

Inventors

• Numata Hidetoshi
• Taira Yoichi
• Tokunari Masao

Classifications

• G02B6/12002

  Three-dimensional structures · CPC title

• G02B6/4204

  the coupling comprising intermediate optical elements, e.g. lenses, holograms (encapsulated active devices H01S5/02208) · CPC title

• B29D11/00663

  Production of light guides · CPC title

• G02B6/423

  using guiding surfaces for the alignment · CPC title

• G02B2006/12147

  Coupler · CPC title