Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Low package parasitic inductance using a thru-substrate interposer
US9370103B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9370103-B2 |
| Application number | US-201314020558-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 6, 2013 |
| Priority date | Sep 6, 2013 |
| Publication date | Jun 14, 2016 |
| Grant date | Jun 14, 2016 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).
First claim
Opening claim text (preview).
What is claimed is: 1. A structure including an interposer having a first side, a second side opposite the first side, a third side, a fourth side opposite the third side, a fifth side, and a sixth side opposite the fifth side, the structure comprising: a plurality of multilayer thin film capacitors comprising a plurality of power and ground terminals disposed in a staggered pattern of rows and columns relative to the third side and the fourth side and relative to the fifth side and the sixth side; and a plurality of conductive vias configured to couple to the staggered pattern between a first set of contacts and a second set of contacts. 2. The structure of claim 1 , wherein the first set of contacts has a smaller pitch than the second set of contacts. 3. The structure of claim 2 , wherein the plurality of multilayer thin film capacitors are disposed between the first set of contacts and the plurality of conductive vias. 4. The structure of claim 3 , further comprising a second plurality of multilayer thin film capacitors formed between the plurality of conductive vias and the second set of contacts. 5. The structure of claim 1 , wherein the plurality of multilayer thin film capacitors are formed in a metal-insulator-metal (MIM) configuration. 6. The structure of claim 5 , wherein the plurality of multilayer thin film capacitors includes a plurality of trench capacitors. 7. The structure of claim 1 , wherein the interposer is a Through Glass Via (TGV) interposer. 8. The structure of claim 1 , wherein the interposer is a Through Silicon Via (TSV) interposer. 9. The structure of claim 1 , wherein the interposer is a ceramic interposer. 10. The structure of claim 1 , wherein the interposer is an organic interposer. 11. The structure of claim 1 , wherein the plurality of multilayer thin film capacitors includes a plurality of trench capacitors.
Assignees
Inventors
Classifications
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
Interconnections or connectors in packages · CPC title
- H10W70/685Primary
comprising multiple insulating layers · CPC title
Package configurations · CPC title
associated with surface mounted components · CPC title
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Frequently asked questions
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- What does patent US9370103B2 cover?
- An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).
- Who is the assignee on this patent?
- Qualcomm Inc, Qualcomm Incorported
- What technology area does this patent fall under?
- Primary CPC classification H10W70/685. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).