Multi-format video decoder with vector processing instructions and methods for use therewith

Patent metadata

Field	Value
Publication number	US-9369713-B2
Application number	US-201414249694-A
Country	US
Kind code	B2
Filing date	Apr 10, 2014
Priority date	Mar 9, 2011
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.

First claim

What is claimed is:

1. A video decoder comprising:
an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal; and
a multi-format video decoding device, coupled to the entropy decoding device, includes at least one vector processor unit for generating a decoded video signal from the EDC data, wherein the at least one vector processor unit is programmed via VPU instructions, wherein at least one of the VPU instructions includes non-vector data and a non-vector processing command to be executed by the at least one vector processor unit and wherein the non-vector processing command includes at least one of: a scalar logical operation on the non-vector data, and a scalar arithmetic operation on the non-vector data, and wherein the VPU instructions include vector data and a vector processing commands to be executed by the at least one vector processor unit and wherein the vector processing commands include mask creation commands, data masking commands, and data move commands.

2. The video decoder of claim 1 wherein the at least one vector processor unit includes at least one matrix vector processor that parallel processes at least one matrix operation of the multi-format video decoding device, and wherein the VPU instructions include at least one matrix command and corresponding matrix data.

3. The video decoder of claim 1 wherein the at least one vector processor unit includes at least one filter vector processor that parallel processes at least one filter operation of the multi-format video decoding device and wherein the VPU instructions include at least one filter command and corresponding filter data.

4. The video decoder of claim 1 wherein the VPU instructions include at least one of: an unconditional branching instruction, and a conditional branching instruction.

5. The video decoder of claim 1 wherein the non-vector processing command is executed in a single instruction of the at least one vector processor unit.

6. The video decoder of claim 1 wherein the encoded video signal is encoded in accordance with a VP8 coding standard.

7. A method comprising:
generating entropy decoded (EDC) data from an encoded video signal;
programming at least one vector processor unit, based on VPU instructions, wherein at least one of the VPU instructions includes non-vector data and a non-vector processing command to be executed by the at least one vector processing unit and wherein the non-vector processing command includes at least one of: a scalar logical operation on the non-vector data, and a scalar arithmetic operation on the non-vector data, and wherein the VPU instructions include vector data and a vector processing commands to be executed by the at least one vector processor unit and wherein the vector processing commands include mask creation commands, data masking commands, and data move commands; and
generating a decoded video signal from the EDC data, via the at least one vector processor unit.

8. The method of claim 7 wherein programming the at least one vector processor unit includes configuring at least one matrix vector processor to parallel process at least one matrix operation, and wherein the VPU instructions include at least one matrix command and corresponding matrix data.

9. The method of claim 7 wherein programming the at least one vector processor unit includes configuring at least one filter vector processor to parallel process at least one filter operation, and wherein the VPU instructions include at least one filter command and corresponding filter data.

10. The method of claim 7 wherein the VPU instructions include at least one of: an unconditional branching instruction, and a conditional branching instruction.

11. The method of claim 7 wherein the non-vector processing command is executed in a single instruction of the at least one vector processing unit.

12. The method of claim 7 wherein the encoded video signal is encoded in accordance with a VP8 coding standard.

13. A video decoder comprising:
a multi-format video decoding device, coupled to receive entropy decoded (EDC) data from an entropy decoding device, wherein the multi-format video decoding device includes:
at least one vector processor unit for generating a decoded video signal from the EDC data, wherein the at least one vector processor unit is programmed via VPU instructions, wherein at least one of the VPU instructions includes non-vector data and a non-vector processing command to be executed by the at least one vector processor unit and wherein the non-vector processing command includes at least one of: a scalar logical operation on the non-vector data, and a scalar arithmetic operation on the non-vector data, and wherein the VPU instructions include vector data and a vector processing commands to be executed by the at least one vector processor unit and wherein the vector processing commands include mask creation commands, data masking commands, and data move commands.

14. The video decoder of claim 13 wherein the at least one vector processor unit includes at least one matrix vector processor that parallel processes at least one matrix operation of the multi-format video decoding device, and wherein the VPU instructions include at least one matrix command and corresponding matrix data.

15. The video decoder of claim 13 wherein the at least one vector processor unit includes at least one filter vector processor that parallel processes at least one filter operation of the multi-format video decoding device and wherein the VPU instructions include at least one filter command and corresponding filter data.

16. The video decoder of claim 13 wherein the VPU instructions include at least one of: an unconditional branching instruction, and a conditional branching instruction.

17. The video decoder of claim 12 wherein the non-vector processing command is executed in a single instruction of the at least one vector processor unit.

18. The video decoder of claim 12 wherein the encoded video signal is encoded in accordance with a VP8 coding standard.

Assignees

• Vixs Systems Inc

Inventors

• Laksono Indra
• Yang Kai
• Wang Hongri
• Liu Dong
• Zhao Xu Gang
• Young Eric
• Hong Edward

Classifications

• H04N19/436

  using parallelised computational arrangements · CPC title

• H04N19/91

  Entropy coding, e.g. variable length coding [VLC] or arithmetic coding · CPC title

• H04N19/44 Primary

  Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder · CPC title

• H04N19/103 Primary

  Selection of coding mode or of prediction mode · CPC title

• H04N19/136

  Incoming video signal characteristics or properties · CPC title