Distribution of an electronic reference clock signal that includes delay and validity information

Patent metadata

Field	Value
Publication number	US-9369225-B2
Application number	US-201213632230-A
Country	US
Kind code	B2
Filing date	Oct 1, 2012
Priority date	Oct 1, 2012
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

An integrated circuit has a clock subsystem, and a circuit. The clock subsystem is configured to provide a reference clock signal to a first module and a second module. The circuit is configured to distribute information describing characteristics of the reference clock signal to the second module. The information distributed with the circuit enables the second module to adapt the reference clock signal based on the information.

First claim

What is claimed is:

1. An integrated circuit comprising:
a clock subsystem configured to provide a reference clock signal to a first module and a second module; and
a circuit configured to distribute information describing characteristics of the reference clock signal to the second module,
wherein the information distributed with the circuit enables the second module to adapt the reference clock signal based on the information and includes delay and validity information indicating when and whether the reference clock signal is valid and timing information on when a frequency of the reference clock signal changes.

2. The integrated circuit of claim 1 , wherein the first module is a mobile communication standard configured to synchronize to a base station in a mobile communication network.

3. The integrated circuit of claim 2 wherein the first module is configured to be driven by a voltage-controlled temperature-compensated crystal oscillator (VCTCXO) grade clock signal and the second module is configured to be driven by a temperature-compensated crystal oscillator (TCXO) grade clock signal.

4. The integrated circuit of claim 1 , wherein the second module includes a global navigation satellite system (GNSS) receiver.

5. The integrated circuit of claim 1 , wherein the information is generated by the clock subsystem.

6. The integrated circuit of claim 1 , wherein the information is generated by the first module.

7. The integrated circuit of claim 1 , wherein an algorithm within the second module continuously adapts the second module based on clock quality provided in the information.

8. The integrated circuit of claim 1 , wherein the clock subsystem is integrated into the first module.

9. The integrated circuit of claim 1 , wherein the clock subsystem is a separate module.

10. A method for sharing a clock signal comprising:
distributing a reference clock signal to a first module and a second module;
distributing information to the second module describing characteristics of the reference clock signal and including delay and validity information indicating when and whether the reference clock signal is valid and timing information on when a frequency of the reference clock signal changes; and
adapting the reference clock signal with the information to meet clocking requirements of the second module.

11. The method of claim 10 , further comprising
synchronizing the reference clock signal to a base station in a mobile communication network.

12. The method of claim 10 ,
wherein the reference clock signal is generated with a oscillating signal from a voltage-controlled temperature-compensated crystal oscillator (VCTCXO) or a crystal oscillator (XO);
wherein the information comprises a frequency correction value configured to adjust a digital to analog converter (DAC); and
wherein adapting the reference clock signal comprises adjusting the digital to analog converter (DAC) with the frequency correction value of the information, and low-pass filtering the reference clock signal with a digital filter.

13. The method of claim 10 , wherein an algorithm within the second module continuously adapts the second module based on clock quality provided in the information.

14. The method of claim 10 , wherein the reference clock signal is generated within the first module.

15. The method of claim 10 , wherein the reference clock signal is generated within separate clock subsystem module.

Assignees

• Intel Mobile Comm Gmbh
• Intel Deutschland Gmbh

Inventors

• Hammes Markus
• Schultz Christoph
• Valori Edoardo
• Wilhelm Michael
• Yan Junlin

Classifications

• H04B1/16

  Circuits · CPC title

• H04B2001/0491

  with frequency synthesizers, frequency converters or modulators · CPC title

• H04B1/0082

  with a common local oscillator for more than one band · CPC title

• H04B1/04

  Circuits · CPC title

• H04J3/0685 Primary

  Clock or time synchronisation in a node; Intranode synchronisation · CPC title