Adjustable and buffered reference for ADC resolution and accuracy enhancements

US9369147B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9369147-B2
Application numberUS-201414491633-A
CountryUS
Kind codeB2
Filing dateSep 19, 2014
Priority dateJul 3, 2014
Publication dateJun 14, 2016
Grant dateJun 14, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: an analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core. 2. The apparatus of claim 1 , wherein a resolution of the ADC core is mapped to an effective number of bits of a targeted signal input range. 3. The apparatus of claim 1 , wherein the ADC core is a ten bit ADC core. 4. The apparatus of claim 1 , wherein the reference voltage generator comprises a voltage reference multiplexer. 5. The apparatus of claim 4 , wherein the voltage reference multiplexer comprises a resistive ladder. 6. An apparatus, comprising: means for performing an analog to digital conversion; a reference voltage generator coupled to an input of the means for performing the analog to digital conversion; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the means for performing the analog to digital conversion. 7. The apparatus of claim 6 , wherein a resolution of the means for performing the analog to digital conversion is mapped to an effective number of bits of a targeted signal input range. 8. The apparatus of claim 6 , wherein the means for performing the analog to digital conversion is a ten bit ADC core. 9. The apparatus of claim 6 , wherein the reference voltage generator comprises a voltage reference multiplexer. 10. The apparatus of claim 6 , wherein the voltage reference multiplexer comprises a resistive ladder.

Assignees

Inventors

Classifications

  • Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

  • Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

  • H03M1/34Primary

    Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

  • H03M1/182Primary

    the feedback signal controlling the reference levels of the analogue/digital converter · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9369147B2 cover?
An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.
Who is the assignee on this patent?
Texas Instruments Deutschland, Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H03M1/34. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).