Multi-channel time-interleaved analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9369142-B2
Application number	US-201514747691-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Jun 25, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

The present invention provides a multi-channel time-interleaved analog-to-digital converter, including: a clock generation circuit, configured to generate a work clock of the analog-to-digital converter; a channel ADC group, including M ADC channels, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals; a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels; a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected, compensation and reconstruction on the digital output signals output by the channel ADC group; and a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit.

First claim

What is claimed is:

1. A multi-channel time-interleaved analog-to-digital converter (ADC), comprising:
a clock generation circuit, configured to generate a work clock of the analog-to-digital converter;
a channel ADC group, comprising M ADC channels, arranged to be in a time-interleaved architecture, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals, wherein M is an integer not less than 2, wherein sampling clocks of ADCs of adjacent subchannels in the M ADC channels have a phase difference of 2π/M;
a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels, to obtain a timing skew parameter of each ADC channel relative to a reference ADC channel;
a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected by the channel mismatch detection circuit, compensation and reconstruction on the digital output signals output by the channel ADC group; and
a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit, to obtain one final high-speed digital output signal.

2. The multi-channel time-interleaved analog-to-digital converter according to claim 1 , wherein the channel mismatch detection circuit further comprises:
a notch filter, configured to perform notch filtering on the output signals of the M ADC channels;
a mismatch error discriminator, configured to perform mismatch error discrimination according to an output result of the notch filter;
an alpha filter, configured to perform smooth filtering on the timing skew parameter generated by the mismatch error discriminator; and
a mismatch error adaptive iterative circuit, configured to optimize an adaptive error value obtained through the smooth filtering, to obtain a timing skew error steady state value.

3. The multi-channel time-interleaved analog-to-digital converter according to claim 2 , wherein the notch filter comprises:
a first shift register, configured to shift an input signal to the right by 6 bits;
a first delay circuit, configured to delay the input signal by one clock;
a second shift register, configured to shift an output signal of the first delay circuit to the right by 6 bits;
a first subtracter, configured to subtract an output of the first shift register from the input signal;
a second subtracter, configured to subtract an output of the second shift register from an output of the first delay circuit;
a first adder, configured to add an output of the second subtracter to an output of the first subtracter;
a second delay circuit, configured to delay an output signal of the first adder by a clock cycle;
a third shift register, configured to shift an output signal of the second delay circuit to the right by 6 bits;
a third subtracter, configured to subtract an output of the third shift register from an output of the second delay circuit; and
a third delay circuit, configured to delay an output of the third subtracter by a clock cycle, and use a delayed output as a final output signal of the notch filter.

4. The multi-channel time-interleaved analog-to-digital converter according to claim 2 , wherein the mismatch error discriminator comprises:
a fourth subtracter, configured to subtract x′% i−1 (n) from a signal x′% i+1 (n) output by the notch filter; and
a first multiplier, configured to multiply an output of the fourth subtracter by a signal x ′ i (n) output by the notch filter,
wherein n is time, i=1, 2, . . . , M−1, and M is a natural number not less than 2.

5. The multi-channel time-interleaved analog-to-digital converter according to claim 2 , wherein the alpha filter comprises:
a fifth subtracter, configured to subtract δ′ i (n−1) from an output signal δ′% i (n) of the mismatch error discriminator;
a second multiplier, configured to multiply an output result of the fifth subtracter by an α factor;
a second adder, configured to add an output of the second multiplier and δ′ i (n); and
a fourth delay circuit, configured to delay an output of the second adder by a clock cycle,
wherein n is time, i=1, 2, . . . , M−1, and M is a natural number not less than 2.

6. The multi-channel time-interleaved analog-to-digital converter according to claim 2 , wherein the mismatch error adaptive iterative circuit comprises:
a first operation circuit, configured to take a maximum value of a mismatch error value δ′ i of each channel output by the alpha filter;
a second operation circuit, configured to take the reciprocal of an output result of the first operation circuit;
a fifth delay circuit, configured to delay an output result of the second operation circuit by a clock cycle;
a third multiplier, configured to multiply an output of the fifth delay circuit by an output signal δ′ i (n) of the alpha filter;
a sixth delay circuit, configured to delay an output result of the third multiplier by a clock cycle;
a fourth multiplier, configured to multiply an output result of the sixth delay circuit by a constant μ;
a third adder, configured to add an output of the fourth multiplier to an output at a previous moment of the mismatch error adaptive iterative circuit; and
a seventh delay circuit, configured to delay an output result of the third adder by a clock cycle, and use a delayed output result as a final timing skew error steady state value δ′ i (n),
wherein n is time, i=1, 2, . . . , M−1, and M is a natural number not less than 2.

7. The multi-channel time-interleaved analog-to-digital converter according to claim 2 , further comprising an energy detector, wherein the energy detector is configured to perform an absolute value operation on an output value of a reference channel, then subtract a set threshold after performing filtering using the alpha filter, and transmit, as a final output to the mismatch error discriminator, a symbol of an operation result obtained after the set threshold has been subtracted, wherein when a high level is output, the mismatch error discriminator works normally, and when a low level is output, a current parameter is blocked, and a previous discrimination value is used.

8. The multi-channel time-interleaved analog-to-digital converter according to claim 2 , further comprising a timing control circuit, configured to control a work process of the analog-to-digital converter.

Assignees

• Huawei Tech Co Ltd

Inventors

• Qiu Bingsen

Classifications

• H03M1/0631 Primary

  Smoothing · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• H03M1/1061

  using digitally programmable trimming circuits · CPC title

• H03M1/0624

  by synchronisation · CPC title