Duty cycle correction circuit and semiconductor device

Patent metadata

Field	Value
Publication number	US-9369118-B2
Application number	US-201414484908-A
Country	US
Kind code	B2
Filing date	Sep 12, 2014
Priority date	Jul 11, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

According to one embodiment, there is provided a duty cycle correction circuit including an input inverter, an output inverter, a charge distribution unit, and a drawing-off unit. The input inverter includes a PMOS transistor and an NMOS transistor and receives a clock signal. The output inverter outputs a clock signal according to a signal transmitted via a signal line from the input inverter. The charge distribution unit distributes, when one transistor of the PMOS transistor and the NMOS transistor is turned on, charge to capacitance elements selected from among one or more first capacitance elements placed on side of the signal line and among a plurality of second capacitance elements disposed on side of source of the one transistor. The drawing-off unit draws off the distributed charge from the selected capacitance elements while the one transistor is maintained to be on.

First claim

What is claimed is:

1. A duty cycle correction circuit comprising:
an input inverter that includes a PMOS transistor and an NMOS transistor and receives a clock signal;
an output inverter that outputs a clock signal according to a signal transmitted via a signal line from the input inverter;
a charge distribution unit that distributes, when one transistor of the PMOS transistor and the NMOS transistor is turned on, charge to capacitance elements selected from among one or more first capacitance elements placed on side of the signal line and among a plurality of second capacitance elements disposed on side of source of the one transistor; and
a drawing-off unit that draws off the distributed charge from the selected capacitance elements while the one transistor is maintained to be on.

2. The duty cycle correction circuit according to claim 1 , wherein the charge distribution unit has:
a plurality of the first capacitance elements disposed on the side of the signal line;
a first selecting unit that selects first capacitance elements to be used for duty cycle adjustment from among the plurality of first capacitance elements to connect to the signal line;
the plurality of second capacitance elements; and
a second selecting unit that selects second capacitance elements to be used for duty cycle adjustment from among the plurality of second capacitance elements to connect to a node on the side of the source of the one transistor.

3. The duty cycle correction circuit according to claim 2 , wherein the first selecting unit has a plurality of first switches corresponding to the plurality of first capacitance elements, and
wherein the second selecting unit has a plurality of second switches corresponding to the plurality of second capacitance elements.

4. The duty cycle correction circuit according to claim 3 , wherein
the plurality of first switches connect selected first capacitance elements from among the plurality of first capacitance elements to the signal line, and
wherein the plurality of second switches connect selected second capacitance elements from among the plurality of second capacitance elements to a node on the side of the source of the one transistor.

5. The duty cycle correction circuit according to claim 4 , wherein
each of the plurality of first capacitance elements has one end connected to the first switch and other end connected to a reference potential or a power supply potential, and
wherein each of the plurality of second capacitance elements has one end connected to the second switch and other end connected to a reference potential or a power supply potential.

6. The duty cycle correction circuit according to claim 2 , wherein
the first selecting unit and the second selecting unit adjust edge timings of a clock signal according to at least total capacitance of selected second capacitance elements.

7. The duty cycle correction circuit according to claim 6 , wherein
the first selecting unit and the second selecting unit select capacitance elements to be used for duty cycle adjustment such that sum of total capacitance of selected first capacitance elements and total capacitance of selected second capacitance elements becomes a target value.

8. The duty cycle correction circuit according to claim 7 , wherein
each of the plurality of first capacitance elements and each of the plurality of second capacitance elements have substantially a same capacitance, and
wherein the first selecting unit and the second selecting unit select capacitance elements to be used for duty cycle adjustment such that sum of number of selected first capacitance elements and number of selected second capacitance elements becomes a target number.

9. The duty cycle correction circuit according to claim 7 , wherein
the drawing-off unit includes a current source that draws off the distributed charge.

10. The duty cycle correction circuit according to claim 1 , wherein
the charge distribution unit has:
the first capacitance element connected to the signal line;
the plurality of second capacitance elements; and
a second selecting unit that selects second capacitance elements to be used for duty cycle adjustment of edge timings of a clock signal from among the plurality of second capacitance elements to connect to a node on the side of the source of the one transistor.

11. The duty cycle correction circuit according to claim 10 , wherein
the second selecting unit has a plurality of second switches corresponding to the plurality of second capacitance elements.

12. The duty cycle correction circuit according to claim 11 , wherein
the first capacitance element has one end connected to the signal line and other end connected to a reference potential or a power supply potential, and
wherein each of the plurality of second capacitance elements has one end connected to the second switch and other end connected to a reference potential or a power supply potential.

13. The duty cycle correction circuit according to claim 1 , wherein
the drawing-off unit has a current source that draws off the distributed charge, and
wherein the duty cycle correction circuit further comprises a potential limiting unit that limits a potential on a node between the source of the one transistor and the current source.

14. The duty cycle correction circuit according to claim 13 , wherein
the potential limiting unit includes a transistor that receives a fixed bias at a gate thereof.

15. The duty cycle correction circuit according to claim 1 , wherein
the output inverter is a Schmitt circuit.

16. A semiconductor device comprising:
a clock generator that generates a clock signal;
a first duty cycle correction circuit that is the duty cycle correction circuit according to claim 1 and receives the clock signal from the clock generator;
an inverter that logically inverts a clock signal output from the first duty cycle correction circuit to generate an inverted clock signal; and
a second duty cycle correction circuit that is the duty cycle correction circuit according to claim 1 and receives the inverted clock signal.

17. A semiconductor device comprising:
a clock generator that generates a clock signal;
a first duty cycle correction circuit that is the duty cycle correction circuit according to claim 1 and receives the clock signal from the clock generator;
an inverter that receives the clock signal from the clock generator and logically inverts to generate an inverted clock signal;
a third duty cycle correction circuit that is the duty cycle correction circuit according to claim 1 and receives the inverted clock signal;
a selecting unit that selects an output of the first duty cycle correction circuit at a first timing and an output of the third duty cycle correction circuit at a second timing to generate an intermediate signal; and
a generating unit that generates an adjusted clock signal using the generated intermediate signal.

18. A semiconductor device comprising:
a clock generator that generates a clock signal;
the duty cycle correction circuit according to claim 1 that receives the clock signal from the clock generator and adjusts duty ratio of the received clock signal to supply to a memory;
a receiver circuit that receives a strobe signal according to the supplied clock signal from the memory;
a duty cycle detection circuit that detects duty ratio of the received strobe signal; and
a control circuit that controls operation of the duty cycle correction circuit so that duty ratio detected by the duty cycle detection circuit t

Assignees

• Toshiba Kk

Inventors

• Nakata Masashi

Classifications

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K5/04

  by increasing duration; by decreasing duration · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K5/07

  by the use of resonant circuits · CPC title