Graphene/nanostructure FET with self-aligned contact and gate

Patent metadata

Field	Value
Publication number	US-9368599-B2
Application number	US-82034110-A
Country	US
Kind code	B2
Filing date	Jun 22, 2010
Priority date	Jun 22, 2010
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.

First claim

The invention claimed is:

1. A method for forming a field effect transistor (FET), the method comprising:
depositing a channel material on an insulator layer of a substrate, the insulator layer having a substantially uniform thickness across a semiconductor layer of the substrate, the channel material comprises a plurality of carbon nanotubes configured in a nonparallel arrangement;
forming a gate over a first portion of the carbon nanotube channel material;
forming spacers, having substantially vertical sidewalls, on and in contact with a second portion of the carbon nanotube channel material adjacent to the gate, the second portion of the carbon nanotube channel material including undoped carbon nanotube channel material;
depositing a layer of contact material over the carbon nanotube channel material, gate, spacers, the substantially vertical sidewalls of the spacers, and the insulator layer of the substrate, such that a portion of the layer of contact material conforms to, and is in contact with the substantially vertical sidewalls of the spacers;
depositing a layer of dielectric material over the layer of contact material, the layer of dielectric material being deposited using a directional deposition process that deposits the layer of dielectric material on substantially horizontal portions of the contact material without depositing the dielectric material on substantially vertical portions of the contact material partially defined by the substantially vertical sidewalls of the spacers;
removing a portion of the layer of dielectric material and a portion of the layer of contact material to expose the gate;
recessing a portion of the layer of contact material located adjacent to the spacers to expose at least a portion of a sidewall of the spacers;
removing the dielectric material; and
patterning the layer of contact material to form a self-aligned contact for the FET, the self-aligned contact being disposed directly on a source region and a drain region of the FET, the source region and the drain region comprising any portion of the carbon nanotube channel material not covered by the gate or the spacers, wherein the patterning comprises removing any portion of the layer of contact material that is not in contact with the FET regions of the substrate such that a sidewall end portion of the carbon nanotube channel material is covered by the remaining portion of the layer of contact material.

2. The method of claim 1 , wherein the spacers comprise one of a nitride and an oxide.

3. The method of claim 1 , wherein the insulator layer comprises an oxide layer, and the channel material is deposited on the oxide layer.

4. The method of claim 1 , wherein the contact material comprises one of a carbon and silicon.

5. The method of claim 4 , further comprising converting the contact material into a carbide or a silicide before patterning the contact material to form the FET.

6. The method of claim 5 , wherein converting the contact material into a carbide or a silicide comprises:
depositing a metal layer over the contact material;
annealing the metal layer and contact material at a temperature higher than a formation temperature of the silicide or carbide, such that the metal layer reacts with the contact material to form the silicide or carbide; and
removing an unreacted portion of the metal layer selective to the silicide or carbide.

7. The method of claim 1 , wherein the dielectric material comprises a material selected such that the contact material may be removed without removing the dielectric material.

8. The method of claim 1 , wherein the dielectric material comprises high density plasma oxide, and the contact material comprises carbon.

9. The method of claim 8 , wherein recessing the contact material comprises use of oxygen plasma.

10. The method of claim 1 , wherein removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate comprises chemical mechanical polishing (CMP).

Assignees

• Chang Josephine
• Lauer Isaac
• Sleight Jeffrey
• IBM

Inventors

• Chang Josephine
• Lauer Isaac
• Sleight Jeffrey

Classifications

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title