Semiconductor device

Patent metadata

Field	Value
Publication number	US-9368551-B2
Application number	US-201514789370-A
Country	US
Kind code	B2
Filing date	Jul 1, 2015
Priority date	Jan 23, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A semiconductor device includes a first fin-shaped semiconductor layer on a semiconductor substrate, a first insulating film around the first fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer, a first gate insulating film around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer, a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer, a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, a first contact electrode surrounding the third gate insulating film, a second contact electrode that connects an upper portion of the first contact electrode to an upper portion of the first pillar-shaped semiconductor layer, and a first magnetic tunnel junction memory element on the second contact electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first fin-shaped semiconductor layer on a semiconductor substrate;
a first insulating film around the first fin-shaped semiconductor layer;
a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer;
a first gate insulating film around the first pillar-shaped semiconductor layer;
a first gate line around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer;
a diffusion layer in a lower portion of the first pillar-shaped semiconductor layer;
a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer;
a first contact electrode surrounding the third gate insulating film,
wherein an upper portion of the first contact electrode is electrically connected to the upper portion of the first pillar-shaped semiconductor layer; and
a first magnetic tunnel junction memory element electrically connected to the upper portion of the first pillar-shaped semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the first contact electrode is composed of a metal having a work function in the range of 4.0 eV to 4.2 eV.

3. The semiconductor device according to claim 1 , wherein the first contact electrode is composed of a metal having a work function in the range of 5.0 eV to 5.2 eV.

4. The semiconductor device according to claim 1 , further comprising a first bit line extending in a direction perpendicular to the first gate line and connected to an upper portion of the first magnetic tunnel junction memory element.

5. A semiconductor device comprising:
a first fin-shaped semiconductor layer on a semiconductor substrate;
a first insulating film around the first fin-shaped semiconductor layer;
a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer;
a first gate insulating film around the first pillar-shaped semiconductor layer;
a first gate line around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer;
a diffusion layer in a lower portion of the first pillar-shaped semiconductor layer;
a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer;
a first contact electrode surrounding the third gate insulating film,
wherein an upper portion of the first contact electrode is electrically connected to the upper portion of the first pillar-shaped semiconductor layer; and
a first magnetic tunnel junction memory element electrically connected to the upper portion of the first pillar-shaped semiconductor layer.

6. The semiconductor device according to claim 5 , wherein the first gate line and the second gate line are each composed of a metal.

7. The semiconductor device according to claim 5 , wherein a width of the first pillar-shaped semiconductor layer in a direction perpendicular to the first fin-shaped semiconductor layer is equal to a width of the first fin-shaped semiconductor layer in the direction perpendicular to the first fin-shaped semiconductor layer.

8. The semiconductor device according to claim 5 , further comprising a first gate insulating film around and at a bottom portion of the first gate line.

Assignees

• Unisantis Elect Singapore Pte

Inventors

• Masuoka Fujio
• Nakamura Hiroki

Classifications

• H10D84/834 Primary

  comprising FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title