Array substrate, manufacturing method thereof and display device

Patent metadata

Field	Value
Publication number	US-9368520-B2
Application number	US-201414568699-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Aug 22, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

The present invention provides array substrate, manufacturing method thereof, and display device, relating to manufacturing technology field of liquid crystal display. The array substrate of the present invention includes: a base substrate, on which a plurality of gate lines and a plurality of data lines are provided; shielding electrodes, which are provided above and electrically insulated from the data lines, and the shielding electrodes at least partially cover the data lines; first electrodes, which are provided in the same layer as the shielding electrodes and are electrically insulated from the shielding electrodes; second electrodes, which are provided above and electrically insulated from the first electrodes, wherein, the shielding electrodes are applied with a shielding voltage signal, the second electrodes are applied with a stable voltage signal, and no electric field or weak electric filed is formed between the shielding electrodes and the second electrodes.

First claim

The invention claimed is:

1. An array substrate, comprising:
a base substrate, on which a plurality of gate lines and a plurality of data lines are provided;
shielding electrodes, which are provided above and electrically insulated from the data lines, the shielding electrodes at least partially covering the data lines;
first electrodes, which are provided in the same layer as the shielding electrodes and are electrically insulated from the shielding electrodes; and
second electrodes, which are provided above and electrically insulated from the first electrodes, wherein,
the shielding electrodes are applied with a shielding voltage signal, the second electrodes are applied with a stable voltage signal, and no electric field or weak electric filed is formed between the shielding electrodes and the second electrodes; and
each data line comprises a plurality of data line bodies and a plurality of connection parts, each connection part is used for connecting two adjacent data line bodies, the array substrate further comprises a first insulation layer, which is provided above the gate lines, wherein,
the data line bodies and the gate lines are provided in the same layer, and the connection parts connect every two adjacent data line bodies in the data lines through via holes penetrating through the first insulation layer.

2. The array substrate of claim 1 , wherein, the shielding electrodes are provided above the data line bodies, and projections of the shielding electrodes on the base substrate completely coincide with those of the data line bodies on the base substrate.

3. The array substrate of claim 1 , wherein, the connection parts and sources and drains of the array substrate are provided in the same layer and employ the same material.

4. The array substrate of claim 1 , wherein, the array substrate further comprises an interlayer insulation layer, the data lines and the gate lines intersect with each other and are separated by the interlayer insulation layer.

5. The array substrate of claim 4 , wherein, projections of the shielding electrodes on the base substrate completely coincide with those of the data lines on the base substrate.

6. The array substrate of claim 1 , wherein, the first electrodes are plate-shaped electrodes and the second electrodes are slit electrodes.

7. The array substrate of claim 6 , wherein, the array substrate further comprise a second insulation layer, which is provided between the first electrodes and the second electrodes to electrically insulate the first electrodes from the second electrodes, and projections of gaps between second electrodes on the base substrate are covered by projections of the data lines on the base substrate.

8. The array substrate of claim 7 , wherein, the plate-shaped electrodes are pixel electrodes, and the slit electrodes are common electrodes; or
the plate-shaped electrodes are common electrodes, and the slit electrodes are pixel electrodes.

9. A manufacturing method of an array substrate, comprising steps of:
forming a plurality of gate lines and a plurality of data lines on a base substrate; and
sequentially forming, on the base substrate with the plurality of gate lines and the plurality of data lines formed thereon, shielding electrodes, first electrodes and second electrodes, wherein,
the shielding electrodes are provided above and electrically insulated from the data lines, and the shielding electrodes at least partially cover the data lines; the first electrodes are provided in the same layer as the shielding electrodes and are electrically insulated from the shielding electrodes; the second electrodes are provided above and electrically insulated from the first electrodes; and no electric field or weak electric filed is formed between the shielding electrodes and the second electrodes; and
each data line comprises a plurality of data line bodies and a plurality of connection parts, each connection part is used for connecting two adjacent data line bodies, wherein
the step of forming a plurality of gate lines and a plurality of data lines on a base substrate specifically comprises steps of:
forming the data line bodies of the data lines and the gate lines on the base substrate by one patterning process;
forming a first insulation layer on the base substrate subjected to the above step;
forming, on the base substrate subjected to the above steps, via holes penetrating through the first insulation layer by a patterning process; and
forming, on the base substrate subjected to the above steps, connection parts of the data lines through a patterning process, so that adjacent data line bodies in each data line are connected to each other through the via holes by the connection parts.

10. The manufacturing method of an array substrate of claim 9 , wherein sources and drains of the array substrate are formed while forming the connection parts of the data lines.

11. The manufacturing method of an array substrate of claim 9 , wherein, the step of forming a plurality of gate lines and a plurality of data lines on a base substrate specifically comprises steps of:
forming, on the base substrate, the plurality of gate lines by a patterning process;
forming an interlayer insulation layer on the base substrate with the gate lines formed thereon; and
forming, on the base substrate with the interlayer insulation layer formed thereon, the plurality of data lines by a patterning process.

12. A display device, comprising an array substrate, wherein the array substrate comprises:
a base substrate, on which a plurality of gate lines and a plurality of data lines are provided;
shielding electrodes, which are provided above and electrically insulated from the data lines, the shielding electrodes at least partially covering the data lines;
first electrodes, which are provided in the same layer as the shielding electrodes and are electrically insulated from the shielding electrodes; and
second electrodes, which are provided above and electrically insulated from the first electrodes, wherein,
the shielding electrodes are applied with a shielding voltage signal, the second electrodes are applied with a stable voltage signal, and no electric field or weak electric filed is formed between the shielding electrodes and the second electrodes; and
each data line comprises a plurality of data line bodies and a plurality of connection parts, each connection part is used for connecting two adjacent data line bodies, the array substrate further comprises a first insulation layer, which is provided above the gate lines, wherein,
the data line bodies and the gate lines are provided in the same layer, and the connection parts connect every two adjacent data line bodies in the data lines through via holes penetrating through the first insulation layer.

13. The display device of claim 12 , wherein, the shielding electrodes are provided above the data line bodies, and projections of the shielding electrodes on the base substrate completely coincide with those of the data line bodies on the base substrate.

14. The display device of claim 12 , wherein, the connection parts and sources and drains of the array substrate are provided in the same layer and employ the same material.

15. The display device of claim 12 , wherein, the array substrate further comprises an interlayer insulation layer, the data lines and the gate lines intersect with each other and are separated by the interlayer insulation layer.

16. The display device of claim 15 , wherein, projections of the shielding electrodes on the base substrate completely coincide with those of the dat

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics

Inventors

• Li Xin
• Zhang Ying
• Pei Yang
• Ding Jinbo
• Wang Jing

Classifications

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• H01L27/127

  Electricity · mapped topic