Forming fins of different materials on the same substrate

Patent metadata

Field	Value
Publication number	US-9368492-B2
Application number	US-201314054009-A
Country	US
Kind code	B2
Filing date	Oct 15, 2013
Priority date	Oct 15, 2013
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer.

First claim

The invention claimed is:

1. A method of forming a semiconductor substrate, the method comprising:
providing a semiconductor-on-insulator (SOI) substrate comprising a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer;
forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer;
removing the second portion of the SOI layer to expose a portion of the buried insulator layer;
forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and
forming a semiconductor layer comprising a second semiconductor material on the exposed portion of the base semiconductor layer and the exposed region of the buried insulator layer.

2. The method of claim 1 , wherein the first semiconductor material is different from the second semiconductor material.

3. The method of claim 1 , wherein the first semiconductor material and the second semiconductor material are selected from the group consisting of silicon, silicon-germanium, and carbon-doped silicon.

4. The method of claim 1 , wherein forming a semiconductor layer comprising a second semiconductor material comprises epitaxially growing the second semiconductor material on the exposed portion of the base substrate.

5. The method of claim 4 , wherein the second semiconductor material comprises the same material as the base semiconductor layer.

6. The method of claim 1 , wherein forming a hole in the exposed portion of the buried insulator layer comprises etching a round hole in the buried insulator layer with a diameter of not less than approximately 10 nm.

7. The method of claim 1 , wherein forming a hole in the exposed portion of the buried insulator layer comprises etching a trench with a width of not less than 10 nm in the buried insulator layer.

8. The method of claim 1 , further comprising:
etching the first portion of the SOI layer to form a first fin made of the first semiconductor material; and
etching the semiconductor layer to form a second fin made of the second semiconductor material.

Assignees

• Globalfoundries Inc
• Globalfoundries

Inventors

• Cheng Kangguo
• Khakifirooz Ali
• Reznicek Alexander
• Schepis Dominic J

Classifications

• H10P14/6903

  containing silicon · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D86/215

  comprising FinFETs · CPC title