Semiconductor device and method for forming the same
US-2024395669-A1 · Nov 28, 2024 · US
Stack packages and methods of fabricating the same
US9368482B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9368482-B2 |
| Application number | US-201514935105-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 6, 2015 |
| Priority date | Jul 25, 2013 |
| Publication date | Jun 14, 2016 |
| Grant date | Jun 14, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. The first and second chips are vertically stacked such that the top surface of the second chip body is directly attached to the first insulation layer and the second bumps of the second chip penetrate the first insulation layer of the first chip to pierce the first through electrodes of the first chip.
First claim
Opening claim text (preview).
What is claimed is: 1. A stack package comprising: a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body; and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9368482B2 cover?
- Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include …
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).