Semiconductor devices including a capping layer and methods of forming semiconductor devices including a capping layer

Patent metadata

Field	Value
Publication number	US-9368362-B2
Application number	US-201414284674-A
Country	US
Kind code	B2
Filing date	May 22, 2014
Priority date	Aug 1, 2013
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a metal pattern in an insulating layer,
forming a capping layer on the metal pattern and the insulating layer, the capping layer comprising a first portion on the metal pattern and a second portion on the insulating layer, wherein the first portion of the capping layer comprises a metal nitride and the second portion of the capping layer comprises a metal oxynitride;
removing the second portion of the capping layer to expose a portion of the insulating layer; and
forming a recess region adjacent the metal pattern by removing the portion of the insulating layer that is exposed by the removing of the second portion of the capping layer.

2. The method of claim 1 , wherein:
the first portion of the capping layer has a first etch selectivity with respect to the insulating layer; and
the second portion of the capping layer has a second etch selectivity with respect to the insulating layer.

3. The method of claim 1 , wherein the first portion of the capping layer remains on an uppermost surface of the metal pattern after removing the second portion of the capping layer.

4. The method of claim 1 , wherein forming the capping layer comprises simultaneously forming the first and second portions of the capping layer on the metal pattern and the insulating layer, respectively.

5. The method of claim 1 , wherein the first and second portions of the capping layer include a same metallic element.

6. The method of claim 1 , wherein:
the recess region exposes a sidewall of the metal pattern; and
the method further comprises conformally forming a buffer insulating layer on the sidewall and an uppermost surface of the metal pattern.

7. The method of claim 1 , wherein forming the capping layer comprises:
performing a pre-treatment process on the insulating layer and on the metal pattern;
performing a purge process using an inert gas, after performing the pre-treatment process;
providing a metal source gas to the insulating layer and to the metal pattern, after performing the purge process; and
providing a nitrogen source gas to the insulating layer and to the metal pattern, after providing the metal source gas to the insulating layer and to the metal pattern.

8. The method of claim 7 , wherein the pre-treatment process comprises a plasma treatment process, a reactive precleaning process, an RF precleaning process, a thermal treatment process, or a UV treatment process.

9. The method of claim 1 , wherein:
forming the recess region comprises forming a preliminary recess region by partially recessing the insulating layer; and
the method further comprises forming a protection layer in the preliminary recess region, on the capping layer, and on a portion of a sidewall of the metal pattern.

10. The method of claim 1 , wherein:
the insulating layer comprises a first insulating layer; and
the method further comprises forming a second insulating layer in the recess region and on the metal pattern such that the second insulating layer defines a void in the recess region.

11. The method of claim 1 , wherein:
the insulating layer comprises a first insulating layer;
the method further comprises forming second insulating layer on the metal pattern to define a void in the recess region;
the second insulating layer comprises a porous insulating layer; and
the method further comprises forming the void in the recess region by:
forming a sacrificial layer in the recess region;
forming the porous insulating layer on the sacrificial layer; and
removing the sacrificial layer through pores of the porous insulating layer.

12. A method of fabricating a semiconductor device, the method comprising:
forming a metal pattern in an insulating layer,
forming a capping layer on top surfaces of the metal pattern and the insulating layer, the capping layer comprising a first portion having a first thickness on the metal pattern and a second portion having a second thickness on the insulating layer, wherein the second thickness is different from the first thickness, wherein the first and second portions of the capping layer have different respective chemical compositions, and wherein the first and second portions of the capping layer include a same metallic element;
removing the second portion of the capping layer to expose a portion of the insulating layer; and
forming a recess region adjacent to the metal pattern by recessing the portion of the insulating layer that is exposed by the removing of the second portion of the capping layer.

13. The method of claim 12 , wherein:
the first and second portions of the capping layer comprise a metallic element and nitrogen; and
a nitrogen content of the capping layer is lower in the second portion than in the first portion.

14. The method of claim 12 ,
wherein providing the non-metal source gas comprises providing a nitrogen source gas to the insulating layer and to the metal pattern, after providing the metal source gas, and
wherein the first portion of the capping layer comprises a metal nitride and the second portion of the capping layer comprises a metal oxynitride.

15. A method of fabricating a semiconductor device, the method comprising:
forming metal patterns in an insulating layer;
forming a capping layer including a first portion on top surfaces of the metal patterns and a second portion on a top surface of the insulating layer, the first and second portions of the capping layer having different respective chemical compositions, wherein the first and second portions of the capping layer include a same metallic element;
removing the second portion of the capping layer to form capping patterns on the metal patterns; and
recessing the top surface of the insulating layer, while the capping patterns are on the metal patterns, to form a recess region between the metal patterns.

16. The method of claim 15 , wherein forming the capping layer comprises simultaneously forming the first and second portions of the capping layer on the metal patterns and the insulating layer, respectively.

17. The method of claim 15 ,
wherein forming the capping layer comprises providing a nitrogen source gas to the insulating layer and to the metal patterns, after providing a metal source gas to the insulating layer and to the metal patterns, and
wherein the first portion of the capping layer comprises a metal nitride and the second portion of the capping layer comprises a metal oxynitride.

18. The method of claim 15 , further comprising forming an insulating layer on the metal patterns to define a gap in the recess region.

19. The method of claim 15 , wherein the recessing of the top surface of the insulating layer is performed while at least a plurality of the capping patterns are free of any mask thereon.

20. The method of claim 12 , wherein forming the capping layer comprises:
providing a non-metal source gas to the insulating layer and to the metal pattern after providing a metal source gas to the insulating layer and to the metal pattern.

Assignees

• Rha Sangho
• Baek Jongmin
• You Wookyung
• Ahn Sanghoon
• Lee Nae-In
• Samsung Electronics Co Ltd

Inventors

• Rha Sangho
• Baek Jongmin
• You Wookyung
• Ahn Sanghoon
• Lee Nae-In

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title