Multi-layered capacitor and circuit board mounted with multi-layered capacitor

Patent metadata

Field	Value
Publication number	US-9368280-B2
Application number	US-201314075544-A
Country	US
Kind code	B2
Filing date	Nov 8, 2013
Priority date	Jan 15, 2013
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

Disclosed herein is a multi-layered capacitor, including: an element formed by alternately multi-layering a dielectric layer and an internal electrode; and external terminals disposed at both ends of the element, wherein the dielectric layer disposed at an upper end U and a lower end L of the element is formed of a paraelectric material and the dielectric layer disposed at a central part C of the element is formed of a ferroelectric material.

First claim

What is claimed is:

1. A multi-layered capacitor, comprising:
an element including a dielectric layer and internal electrodes alternately layered in the dielectric layer; and
external terminals disposed at both ends of the element,
wherein the dielectric layer disposed at an upper end and a lower end of the element is formed of a paraelectric material and the dielectric layer disposed at a central part of the element is formed of a ferroelectric material, and
at least one of the upper end and the lower end comprises at least one of the internal electrodes.

2. The multi-layered capacitor according to claim 1 , wherein the ferroelectric material includes any one selected from a group consisting of barium titanate (BaTiO 3 )-based ceramics, Pb-based composite perovskite-based ceramics, strontium titanate (SrTiO 3 )-based ceramics or a mixture of two or more thereof.

3. The multi-layered capacitor according to claim 1 , wherein the paraelectric material includes any one selected from a group consisting of potassium zirconate (CaZrO 3 )-based ceramics, barium zirconate (BaZrO 3 )-based ceramics, and strontium zirconate (SrZrO 3 )-based ceramics or a mixture of two or more thereof.

4. The multi-layered capacitor according to claim 1 , wherein the relationship among a thickness T UPPER of the upper end, a thickness T LOWER of the lower end, and a thickness T CENTER of the central part of the element satisfies the following Equation
( T UPPER −T LOWER ): T CENTER =1:1 to 1:1.5.

5. The multi-layered capacitor according to claim 1 , wherein the upper end of the element includes an upper margin layer formed of only the paraelectric material.

6. The multi-layered capacitor according to claim 1 , wherein the lower end of the element includes a lower margin layer formed of only the paraelectric material.

7. The multi-layered capacitor according to claim 1 , wherein the upper end of the element includes an upper margin layer formed of only the paraelectric material and the lower end of the element includes a lower margin layer formed of only the paraelectric material.

8. The multi-layered capacitor according to claim 5 , wherein the upper margin layer or the lower margin layer is formed by multi-layering the dielectric layer formed of the paraelectric material in plural.

9. A circuit board mounted with a multi-layered capacitor, wherein in a circuit board mounting structure of the multi-layered capacitor,
the multi-layered capacitor includes an element having a dielectric layer and internal electrodes alternately layered in the dielectric layer; and external terminals disposed at both ends of the element,
the dielectric layer disposed at an upper end and a lower end of the element is formed of a paraelectric material and the dielectric layer disposed at a central part of the element is formed of a ferroelectric material, and at least one of the upper end and the lower end comprises at least one of the internal electrodes, and
the external terminals are conductively connected with lands disposed in the circuit board via a conductive material.

10. The circuit board mounted with a multi-layered capacitor according to claim 9 ,
wherein the relationship between a thickness T LOWER of the lower end of the element and a height H SOLDER of the conductive material satisfies the following Equation
T LOWER :H SOLDER =0.5:1 to 1:1.

11. A multi-layered capacitor, comprising:
a capacity portion having a dielectric layer formed of a ferroelectric material and internal electrodes alternately layered in the dielectric layer;
an upper end and a lower end formed of a paraelectric material and comprising at least one of the internal electrodes, and
an upper margin portion disposed in the upper end and a lower margin portion disposed in the lower end, the upper and lower margin portions being formed of the paraelectric material; and
external terminals disposed at both ends of an element configured of the capacity portion and the upper and lower ends.

12. The multi-layered capacitor according to claim 11 , wherein the ferroelectric material includes any one selected from a group consisting of barium titanate (BaTiO 3 )-based ceramics, Pb-based composite perovskite-based ceramics, strontium titanate (SrTiO 3 )-based ceramics or a mixture of two or more thereof.

13. The multi-layered capacitor according to claim 11 , wherein the paraelectric material includes any one selected from a group consisting of potassium zirconate (CaZrO 3 )-based ceramics, barium zirconate (BaZrO 3 )-based ceramics, and strontium zirconate (SrZrO 3 )-based ceramics or a mixture of two or more thereof.

14. The multi-layered capacitor according to claim 11 , wherein the relationship among a thickness T MARGIN21 of the upper margin portion, a thickness T MARGIN22 of the lower margin portion, and a thickness T CAPACITY of the capacity portion satisfies the following Equation
( T MARGIN21 +T MARGIN22 ): T CAPACITY =1:1 to 1:1.5.

15. A circuit board mounted with a multi-layered capacitor, wherein in a circuit board mounting structure of the multi-layered capacitor,
the multi-layered capacitor includes a capacity portion having a dielectric layer formed of a ferroelectric material and internal electrodes alternately layered in the dielectric layer; an upper end and a lower end formed of a paraelectric material and comprising at least one of the internal electrodes; and an upper margin portion disposed in the upper end and a lower margin portion disposed in the lower end, the upper and lower margin portions being formed of the paraelectric material; and external terminals disposed at both ends of an element configured of the capacity portion and the upper and lower ends, and
the external terminals are conductively connected with lands disposed in the circuit board via a conductive material.

16. The circuit board mounted with a multi-layered capacitor according to claim 15 , wherein the relationship between a thickness T MARGIN22 of the lower margin portion and a height H SOLDER of the conductive material satisfies the following Equation
T MARGIN22 :H SOLDER =0.5:1 to 1:1.

17. The multi-layered capacitor according to claim 6 , wherein the upper margin layer or the lower margin layer is formed by multi-layering the dielectric layer formed of the paraelectric material in plural.

18. The multi-layered capacitor according to claim 7 , wherein the upper margin layer or the lower margin layer is formed by multi-layering the dielectric layer formed of the paraelectric material in plural.

Assignees

• Samsung Electro Mech

Inventors

• Park Min Cheol
• Ahn Young Ghyu
• Park Sang Soo
• Cho Joon Yeob

Classifications

• H05K3/346

  Solder materials or compositions specially adapted therefor · CPC title

• H01G4/30

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/1236

  based on zirconium oxides or zirconates (H01G4/1263 takes precedence) · CPC title

• H05K2201/2045

  Protection against vibrations · CPC title

• H05K2201/10015

  Non-printed capacitor · CPC title