Ex-core nuclear instrumentation system

US9368239B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9368239-B2
Application numberUS-201213585184-A
CountryUS
Kind codeB2
Filing dateAug 14, 2012
Priority dateMar 13, 2012
Publication dateJun 14, 2016
Grant dateJun 14, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The ex-core nuclear instrumentation system includes a key hole, and it is configured such that in the state where a key lock switch is inserted into the key hole, writing to a electrically rewritable nonvolatile memory is made valid by a general-purpose logic, and when writing to a electrically rewritable nonvolatile memory is in valid and the operation panel and the FPGA perform a serial communication and in a case where the data order of the serial communication is the predetermined data order, the CPU controls the electrically rewritable nonvolatile memory, and rewriting data, which is outputted from the operation panel, to the electrically rewritable nonvolatile memory is transmitted from the FPGA to the electrically rewritable nonvolatile memory so as to rewrite the data in the electrically rewritable nonvolatile memory.

First claim

Opening claim text (preview).

What is claimed is: 1. An ex-core nuclear instrumentation system, comprising: neutron detectors which measure neutron flux leaked from a reactor vessel and convert the neutron flux into a current value, a detector signal processing circuit which converts the converted current value into a voltage value, a signal processing card which performs arithmetic processing using a voltage value which is converted in the detector signal processing circuit so as to input the state of neutron flux during the operation of the reactor, and an operation panel having a man machine interface, wherein the signal processing card includes a CPU, a FPGA, an electrically rewritable nonvolatile memory and a key switch, wherein the signal processing card has general-purpose logic, which is connected directly to the key switch and controls a write signal of the electrically rewritable nonvolatile memory, that is configured to prevent the writing to electrically nonvolatile memory when a key is removed from the key switch, and when the key is engaged with the key switch the CPU retrieves rewrite data from the operation panel through the FPGA to the electrically rewritable nonvolatile memory to rewrite the data in the electrically rewritable nonvolatile memory. 2. The ex-core nuclear instrumentation system as claimed in claim 1 , wherein the signal processing card and the operation panel are constituted by separate electronic substrates, and the signal processing card and the operation panel are connected by a serial communication line. 3. The ex-core nuclear instrumentation system as claimed in claim 1 , wherein signals which are outputted from the operation panel include signals other than rewriting data to the electrically rewritable nonvolatile memory. 4. The ex-core nuclear instrumentation system as claimed in claim 1 , wherein the electrically rewritable nonvolatile memory is configured to be reset. 5. The ex-core nuclear instrumentation system as claimed in claim 1 , wherein the man machine interface includes an input key.

Assignees

Inventors

Classifications

  • Computer implemented control · CPC title

  • Cross-Sectional Technologies · mapped topic

  • G21C17/108Primary

    Measuring reactor flux · CPC title

  • Energy generation of nuclear origin · CPC title

  • Nuclear fission reactors · CPC title

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Frequently asked questions

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What does patent US9368239B2 cover?
The ex-core nuclear instrumentation system includes a key hole, and it is configured such that in the state where a key lock switch is inserted into the key hole, writing to a electrically rewritable nonvolatile memory is made valid by a general-purpose logic, and when writing to a electrically rewritable nonvolatile memory is in valid and the operation panel and the FPGA perform a serial commu…
Who is the assignee on this patent?
Nagae Tomoyoshi, Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification G21C17/108. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).