Hardware chip select training for memory using write leveling mechanism

Patent metadata

Field	Value
Publication number	US-9368169-B2
Application number	US-201213726926-A
Country	US
Kind code	B2
Filing date	Dec 26, 2012
Priority date	Dec 26, 2012
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.

First claim

What is claimed is:

1. A method of training command signals for a memory module, said method comprising:
a) programming a memory controller into a mode wherein an address signal is driven for a programmable time period;
b) programming a programmable delay line of said address signal with a delay value, such that said address signal is delayed by said delay value;
c) performing initialization of said memory module, wherein all bits except a first bit of said address signal are driven at said memory controller for said programmable time period, and wherein said performing comprises sending a write leveling mode register set command to said memory module from said memory controller by driving said first bit to a first level for a single clock cycle;
d) placing said memory module in a write leveling mode when said first bit is sampled at said memory module at said first level;
e) at said memory controller, performing a write leveling procedure and determining a response thereto from said memory module; and
f) determining whether said memory module is in a pass state or an error state based on said response, wherein said memory module is in said pass state when said response indicates said memory module is in said write leveling mode, and wherein said memory module is in said error state when said response indicates said memory module is not in said write leveling mode.

2. The method of claim 1 further comprising:
resetting said memory module upon a determination that said memory module is in said error state;
reprogramming said programmable delay line with a different delay value; and
repeating said d)-f).

3. The method of claim 1 further comprising determining a range of delay values that result in said memory module determined to be in said pass state.

4. The method of claim 1 wherein a frequency of said memory controller remains constant and wherein further a frequency of said chip select remains constant.

5. The method of claim 1 wherein a plurality of address signals associated with said memory module are held static for a predetermined number of clock cycles.

6. The method of claim 1 wherein:
said memory module is in said pass state when a feedback from said memory module changes from a binary zero to a binary one; and
said memory module is in said error state when said feedback remains a binary zero.

7. The method of claim 1 wherein said placing said memory module in said write leveling mode further comprises sending a mode register set command to said memory module.

8. A non-transitory computer readable storage medium having stored thereon, computer executable instructions that, if executed by a computer system cause the computer system to perform a method of training command signals for a memory module, said method comprising:
a) programming a memory controller into a mode wherein an address signal is driven for a programmable time period;
b) programming a programmable delay line of said address signal with a delay value, such that said address signal is delayed by said delay value;
c) performing initialization of said memory module, wherein all bits except a first bit of said address signal are driven at said memory controller for said programmable time period, and wherein said performing comprises sending a write leveling mode register set command to said memory module from said memory controller by driving said first bit to a first level for a single clock cycle;
d) placing said memory module in a write leveling mode when said first bit is sampled at said memory module at said first level;
e) at said memory controller, performing a write leveling procedure and determining a response thereto from said memory module; and
f) determining whether said memory module is in a pass state or an error state based on said response, wherein said memory module is in said pass state when said response indicates said memory module is in said write leveling mode, and wherein said memory module is in said error state when said response indicates said memory module is not in said write leveling mode.

9. The computer readable storage medium of claim 8 , wherein said method further comprises:
resetting said memory module upon a determination that said memory module is in said error state;
reprogramming said programmable delay line with a different delay value; and
repeating said d)-f).

10. The computer readable storage medium of claim 8 wherein said method further comprises determining a range of delay values that result in said memory module determined to be in said pass state.

11. The computer readable storage medium of claim 8 wherein a frequency of said memory controller remains constant and wherein further a frequency of said chip select remains constant.

12. The computer readable storage medium of claim 8 wherein a plurality of address signals associated with said memory module are held static for a predetermined number of clock cycles.

13. The computer readable storage medium of claim 8 wherein:
said memory module is in said pass state when a feedback from said memory module changes from a binary zero to a binary one; and
said memory module is in said error state when said feedback remains a binary zero.

14. The computer readable storage medium of claim 8 wherein said placing said memory module in said write leveling mode further comprises sending a mode register set command to said memory module.

15. A system comprising:
a processor coupled to a non-transitory computer readable storage media using a bus and executing computer readable code which causes the computer system to perform a method of training command signals for a memory module, said method comprising:
a) programming a memory controller into a mode wherein an address signal is driven for a programmable time period;
b) programming a programmable delay line of said address signal with a delay value, such that said address signal is delayed by said delay value;
c) performing initialization of said memory module, wherein all bits except a first bit of said address signal are driven at said memory controller for said programmable time period, and wherein said performing comprises sending a write leveling mode register set command to said memory module from said memory controller by driving said first bit to a first level for a single clock cycle;
d) placing said memory module in a write leveling mode when said first bit is sampled at said memory module at said first level;
e) at said memory controller, performing a write leveling procedure and determining a response thereto from said memory module; and
f) determining whether said memory module is in a pass state or an error state based on said response, wherein said memory module is in said pass state when said response indicates said memory module is in said write leveling mode, and wherein said memory module is in said error state when said response indicates said memory module is not in said write leveling mode.

16. The system of claim 15 , wherein said method further comprises:
resetting said memory module upon a determination that said memory module is in said error state;
reprogramming said programmable delay line with a different delay value; and
repeating said d)-f).

17. The system of claim 15 wherein said method further comprises determining a range of delay values that result in said memory module determined to be in said pass state.

18. The system of claim 15 wherein:
a frequency of said memory controller remains constant and wherein further a frequency of said chip select remains constant;

Assignees

• Nvidia Corp

Inventors

• Malladi Venkata Ramana
• Cheng Tony Yuhsiang
• Raghava Sharath
• Kumar Ambuj
• Sahni Arunjit
• Lam Paul

Classifications

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title