Display apparatus and method thereof

Patent metadata

Field	Value
Publication number	US-9368084-B2
Application number	US-35109509-A
Country	US
Kind code	B2
Filing date	Jan 9, 2009
Priority date	Jul 21, 2008
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

In the display apparatus, a gate driver receives at least one clock to sequentially provide gate lines in a display panel with a gate signal in a high state corresponding to a high interval of the clock. The gate driver includes a plurality of amorphous silicon transistors and is formed in the display panel through a thin film process. The clock has a delay time of about 2.0 μs or less. If the delay time of the clock is reduced less than about 2.0 μs, a threshold voltage margin of the transistors increases, so that the gate driver may not malfunction in a high temperature aging process. As a result, the gate driver may be prevented from malfunctioning in the high temperature aging process.

First claim

What is claimed is:

1. A display apparatus comprising:
a display panel having gate lines which sequentially receive a gate signal, data lines which receive a data signal, and a plurality of pixels which display an image corresponding to the data signal in response to the gate signal;
a data driver which provides the data signal to the data lines; and
a gate driver provided in the display panel and which receives at least one clock via a clock interconnection to sequentially provide the gate lines with the gate signal in a high state corresponding to a high interval of the clock,
wherein the clock interconnection with the gate driver is configured to provide the clock having a delay time of about 2.0 μs or less,
wherein the gate driver comprises:
a shift register having a plurality of stages connected with each other one after another to sequentially output the gate signal;
a first clock interconnection of the clock interconnection to provide the stages with a first clock;
a second clock interconnection of the clock interconnection to provide the stages with a second clock different from the first clock; and
a plurality of amorphous silicon transistor,
wherein each of the first and second clock interconnections has a thickness of a bout 1500 Å to about 3000 Å,
wherein the transistors have a threshold voltage margin increase of at least 20V in an aging process when the clock interconnection with the gate driver is configured to provide the clock having a delay time of about 2.0 μs or less.

2. The display apparatus of claim 1 , wherein the first clock has an opposite phase to a phase of the second clock, and each of the first and second clocks have a delay time of about 2.0 μs or less.

3. The display apparatus of claim 1 , wherein each of the first and second clock interconnections has a structure, in which at least one layer is laminated.

4. The display apparatus of claim 3 , wherein each of the first and second clock interconnections comprises:
a first interconnection layer containing a gate metal; and
a second interconnection layer containing a data metal.

5. The display apparatus of claim 4 , further comprising an insulating layer interposed between the first and second clock interconnections, wherein the insulating layer is formed with at least one contact hole formed therethrough to expose the first interconnection layer, and the second interconnection layer is electrically connected with the first interconnection layer through the contact hole.

6. The display apparatus of claim 4 , wherein the first interconnection layer and the gate lines are formed in a same layer of the display panel, and the second interconnection layer and the data lines are formed in a same layer of the display panel.

7. The display apparatus of claim 1 , wherein the data driver comprises at least one chip.

8. A method of preventing a gate driver in a display apparatus from malfunctioning due to a high temperature aging process, the display apparatus including a display panel having gate lines to sequentially receive a gate signal, data lines to receive a data signal from a data driver, and a plurality of pixels to display an image corresponding to the data signal in response to the gate signal, the method comprising:
forming a gate driver in the display panel to receive at least one clock via a clock interconnection to sequentially provide the gate lines with the gate signal in a high state corresponding to a high interval of the clock; and,
delivering the clock within the gate driver with a delay time of about 2.0 μs or less based on a configuration of the clock interconnection,
wherein forming the gate driver includes:
forming a shift register having a plurality of stages connected with each other one after another to sequentially output the gate signal;
forming a first clock interconnection providing the stages with a first clock;
forming a second clock interconnection of the clock interconnection providing the stages with a second clock different from the first clock; and
forming a plurality of amorphous silicon transistors,
wherein forming the first and second clock interconnections includes forming each of the first and second clock interconnections with a thickness of about 1500 Å to about 3000 Å,
wherein, during the high temperature ageing process, a threshold voltage margin of transistors in the gate driver is increased by more than about 20V when the clock interconnection with the gate driver is configured to provide the clock having a delay time of about 2.0 μs or less.

9. The method of claim 8 , wherein forming the first clock interconnection includes forming a first interconnection layer in a same layer of the display panel as the gate lines and forming the second clock interconnection includes forming a second interconnection layer in a same layer of the display panel as the data lines.

10. The method of claim 9 , further comprising forming an insulating layer between the first and second interconnection layers, forming the insulating layer with at least one contact hole therethrough to expose the first interconnection layer, and electrically connecting the second interconnection layer with the first interconnection layer through the contact hole.

11. The method of claim 8 , further comprising increasing a thickness of the first and second clock interconnections to reduce the delay time of the first and second clocks to about 2.0 μs or less.

12. The method of claim 8 , further comprising increasing a width of the first and second clock interconnections to reduce the delay time of the first and second clocks to about 2.0 μs or less.

13. The display apparatus of claim 4 , wherein the first interconnection layer and the second interconnection layer are a single layer.

14. The display apparatus of claim 13 , wherein the first interconnection layer and the second interconnection layer is provided in the same layer as the gate lines.

Assignees

• Kwon Ji-Hyun
• Kwon Ho-Kyoon
• Ki Dong-Hyon
• Lee Won-Hee
• Samsung Display Co Ltd

Inventors

• Kwon Ji-Hyun
• Kwon Ho-Kyoon
• Ki Dong-Hyon
• Lee Won-Hee

Classifications

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G09G3/3674 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G02F1/133

  Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) · CPC title